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description the 3803/3804 group is the 8-bit microcomputer based on the 740 family core technology. the 3803/3804 group is designed for household products, office automation equipment, and controlling systems that require ana- log signal processing, including the a-d converter and d-a converters. the 3804 group is the version of the 3803 group to which an i 2 c- bus control function has been added. features l basic machine-language instructions ...................................... 71 l minimum instruction execution time ................................ 0.25 m s (at 16.8 mhz oscillation frequency) l memory size rom ............................................................... 16 k to 32 k bytes (60 k bytes for flash memory version) ram ................................................................. 640 to 1024 bytes (2048 bytes for flash memory version) l programmable input/output ports ............................................ 56 l software pull-up resistors ................................................. built-in l interrupts 21 sources, 16 vectors ............................................... 3803 group (external 8, internal 12, software 1) 23 sources, 16 vectors ............................................... 3804 group (external 9, internal 13, software 1) l timers ........................................................................... 16-bit 5 1 8-bit 5 4 (with 8-bit prescaler) l watchdog timer ............................................................ 16-bit 5 1 l serial i/o ...................... 8-bit 5 2 (uart or clock-synchronized) 8-bit 5 1 (clock-synchronized) l pwm ............................................ 8-bit 5 1 (with 8-bit prescaler) l i 2 c-bus interface (3804 gourp only) ........................... 1 channel l a-d converter ............................................. 10-bit 5 16 channels (8-bit reading enabled) l d-a converter ................................................. 8-bit 5 2 channels l led direct drive port .................................................................. 8 l clock generating circuit ..................................... built-in 2 circuits (connect to external ceramic resonator or quartz-crystal oscillator) l power source voltage in high-, middle-speed mode at 16.8 mhz oscillation frequency ............................ 4.5 to 5.5 v at 12.5 mhz oscillation frequency ............................ 4.0 to 5.5 v at 8.38 mhz oscillation frequency) ........................ 2.7 to 5.5 v ] in low-speed mode at 32 khz oscillation frequency .............................. 2.7 to 5.5 v ] ( ] this value of flash memory version is 4.0 to 5.5 v.) l power dissipation in high-speed mode ................................................ 60 mw (typ.) (at 16.8 mhz oscillation frequency, at 5 v power source voltage) in low-speed mode ................................................... 60 m w (typ.) (at 32 khz oscillation frequency, at 3 v power source voltage) 3803/3804 group single-chip 8-bit cmos microcomputer mitsubishi microcomputers l operating temperature range .................................... C20 to 85 c l packages sp .................................................. 64p4b (64-pin 750 mil sdip) fp ....................................... 64p6n-a (64-pin 14 5 14 mm qfp) hp ..................................... 64p6q-a (64-pin 10 5 10 mm lqfp) l supply voltage ................................................. v cc = 5 v 10 % l program/erase voltage ........................... v pp = 11.7 v to 12.6 v l programming method ...................... programming in unit of byte l erasing method .............................. batch erasing (chip erasing) l program/erase control by software command l number of times for programming/erasing ............................ 100 n notes 1. the specifications of this product are subject to change be- cause it is under development. inquire the use of mitsubishi electric corporation. 2. the flash memory version cannot be used for application em- bedded in the mcu card.
2 3803/3804 group single-chip 8-bit cmos microcomputer mitsubishi microcomputers pin configuration (top view) fig. 1 3803 group pin configuration package type : 64p6n-a/64p6q-a pin configuration (top view) fig. 2 3803 group pin configuration package type : 64p4b 3 2 3 1 3 0 2 9 2 8 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 4 9 5 0 5 1 5 2 5 3 5 4 5 5 5 6 5 7 5 8 5 9 6 0 6 1 6 2 6 3 2 7 6 4 4 8 4 7 4 6 4 5 4 3 4 2 4 1 4 0 3 9 3 8 3 7 3 6 3 5 3 4 3 3 4 4 1 2 3 4 5 6 7 8 9 1 0 1 1 1 2 1 3 1 4 1 5 1 6 p 0 0 / a n 8 p 0 1 / a n 9 p 0 2 / a n 1 0 p 0 3 / a n 1 1 p 0 4 / a n 1 2 p 0 5 / a n 1 3 p 0 6 / a n 1 4 p 0 7 / a n 1 5 p 1 0 / i n t 4 1 p 1 1 / i n t 0 1 p 1 2 p 1 3 p 1 6 p 1 4 p 1 5 p 1 7 p 2 7 ( l e d 7 ) p 2 0 ( l e d 0 ) p 2 1 ( l e d 1 ) p 2 2 ( l e d 2 ) p 2 3 ( l e d 3 ) p 2 4 ( l e d 4 ) p 2 5 ( l e d 5 ) p 2 6 ( l e d 6 ) v s s x o u t x i n p 4 2 / i n t 1 r e s e t c n v s s p 4 0 / i n t 4 0 / x c o u t p 4 1 / i n t 0 0 / x c i n p 3 5 / t x d 3 p 3 4 / r x d 3 p 3 1 / d a 2 p 3 0 / d a 1 v c c v r e f a v s s p 6 7 / a n 7 p 6 6 / a n 6 p 6 5 / a n 5 p 6 4 / a n 4 p 6 3 / a n 3 p 3 7 / s r d y 3 p 3 6 / s c l k 3 p 3 3 p 3 2 p 6 1 / a n 1 p 6 0 / a n 0 p 5 7 / i n t 3 p 5 6 / p w m p 5 5 / c n t r 1 p 5 4 / c n t r 0 p 5 2 / s c l k 2 p 5 1 / s o u t 2 p 5 0 / s i n 2 p 4 6 / s c l k 1 p 4 5 / t x d 1 p 4 4 / r x d 1 p 4 3 / i n t 2 p 6 2 / a n 2 p 4 7 / s r d y 1 / c n t r 2 p 5 3 / s r d y 2 m 3 8 0 3 7 m 8 - x x x f p / h p m 3 8 0 3 9 f f f p / h p v p p : f l a s h m e m o r y v e r s i o n 6 4 6 3 6 2 6 1 6 0 5 9 5 8 5 7 5 6 5 5 5 4 5 3 5 2 5 1 5 0 4 9 4 8 4 7 4 6 4 5 4 2 4 4 4 3 4 1 4 0 3 9 3 8 3 7 3 6 3 5 3 4 3 3 1 2 3 4 5 6 7 8 9 1 0 1 1 1 2 1 3 1 4 1 5 1 6 1 7 1 8 1 9 2 0 2 2 2 3 2 4 2 5 2 6 2 7 2 8 2 9 3 0 3 1 3 2 2 1 m 3 8 0 3 9 f f s p v c c v r e f a v s s p 6 7 / a n 7 p 6 6 / a n 6 p 6 4 / a n 4 p 6 3 / a n 3 p 6 2 / a n 2 p 6 1 / a n 1 p 6 0 / a n 0 p 5 7 / i n t 3 p 5 6 / p w m p 5 5 / c n t r 1 p 5 4 / c n t r 0 p 5 2 / s c l k 2 p 5 1 / s o u t 2 p 5 0 / s i n 2 p 4 6 / s c l k 1 p 4 5 / t x d 1 p 4 4 / r x d 1 p 4 3 / i n t 2 p 4 2 / i n t 1 c n v s s p 4 0 / i n t 4 0 / x c o u t x i n x o u t v s s r e s e t p 3 0 / d a 1 p 3 1 / d a 2 p 3 4 / r x d 3 p 3 5 / t x d 3 p 0 0 / a n 8 p 2 0 ( l e d 0 ) p 5 3 / s r d y 2 p 6 5 / a n 5 p 4 1 / i n t 0 0 / x c i n p 0 1 / a n 9 p 0 2 / a n 1 0 p 0 3 / a n 1 1 p 0 4 / a n 1 2 p 0 5 / a n 1 3 p 0 6 / a n 1 4 p 0 7 / a n 1 5 p 1 0 / i n t 4 1 p 1 1 / i n t 0 1 p 1 2 p 1 3 p 1 4 p 1 5 p 1 6 p 1 7 p 2 1 ( l e d 1 ) p 2 2 ( l e d 2 ) p 2 3 ( l e d 3 ) p 2 4 ( l e d 4 ) p 2 5 ( l e d 5 ) p 2 6 ( l e d 6 ) p 2 7 ( l e d 7 ) p 3 2 p 3 3 p 3 6 / s c l k 3 p 3 7 / s r d y 3 p 4 7 / s r d y 1 / c n t r 2 m 3 8 0 3 7 m 8 - x x x s p v p p : f l a s h m e m o r y v e r s i o n
3 3803/3804 group single-chip 8-bit cmos microcomputer mitsubishi microcomputers pin configuration (top view) fig. 3 3804 group pin configuration package type : 64p6n-a/64p6q-a pin configuration (top view) fig. 4 3804 group pin configuration package type : 64p4b 3 2 3 1 3 0 2 9 2 8 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 4 9 5 0 5 1 5 2 5 3 5 4 5 5 5 6 5 7 5 8 5 9 6 0 6 1 6 2 6 3 2 7 6 4 4 8 4 7 4 6 4 5 4 3 4 2 4 1 4 0 3 9 3 8 3 7 3 6 3 5 3 4 3 3 4 4 1 2 3 4 5 6 7 8 9 1 0 1 1 1 2 1 3 1 4 1 5 1 6 p 0 0 / a n 8 p 0 1 / a n 9 p 0 2 / a n 1 0 p 0 3 / a n 1 1 p 0 4 / a n 1 2 p 0 5 / a n 1 3 p 0 6 / a n 1 4 p 0 7 / a n 1 5 p 1 0 / i n t 4 1 p 1 1 / i n t 0 1 p 1 2 p 1 3 p 1 6 p 1 4 p 1 5 p 1 7 p 2 7 ( l e d 7 ) p 2 0 ( l e d 0 ) p 2 1 ( l e d 1 ) p 2 2 ( l e d 2 ) p 2 3 ( l e d 3 ) p 2 4 ( l e d 4 ) p 2 5 ( l e d 5 ) p 2 6 ( l e d 6 ) v s s x o u t x i n p 4 2 / i n t 1 r e s e t c n v s s p 4 0 / i n t 4 0 / x c o u t p 4 1 / i n t 0 0 / x c i n p 3 5 / t x d 3 p 3 4 / r x d 3 p 3 1 / d a 2 p 3 0 / d a 1 v c c v r e f a v s s p 6 7 / a n 7 p 6 6 / a n 6 p 6 5 / a n 5 p 6 4 / a n 4 p 6 3 / a n 3 p 3 7 / s r d y 3 p 3 6 / s c l k 3 p 3 3 / s c l p 3 2 / s d a p 6 1 / a n 1 p 6 0 / a n 0 p 5 7 / i n t 3 p 5 6 / p w m p 5 5 / c n t r 1 p 5 4 / c n t r 0 p 5 2 / s c l k 2 p 5 1 / s o u t 2 p 5 0 / s i n 2 p 4 6 / s c l k 1 p 4 5 / t x d 1 p 4 4 / r x d 1 p 4 3 / i n t 2 p 6 2 / a n 2 p 4 7 / s r d y 1 / c n t r 2 p 5 3 / s r d y 2 m 3 8 0 4 7 m 8 - x x x f p / h p m 3 8 0 4 9 f f f p / h p v p p : f l a s h m e m o r y v e r s i o n 6 4 6 3 6 2 6 1 6 0 5 9 5 8 5 7 5 6 5 5 5 4 5 3 5 2 5 1 5 0 4 9 4 8 4 7 4 6 4 5 4 2 4 4 4 3 4 1 4 0 3 9 3 8 3 7 3 6 3 5 3 4 3 3 1 2 3 4 5 6 7 8 9 1 0 1 1 1 2 1 3 1 4 1 5 1 6 1 7 1 8 1 9 2 0 2 2 2 3 2 4 2 5 2 6 2 7 2 8 2 9 3 0 3 1 3 2 2 1 m 3 8 0 4 9 f f s p v c c v r e f a v s s p 6 7 / a n 7 p 6 6 / a n 6 p 6 4 / a n 4 p 6 3 / a n 3 p 6 2 / a n 2 p 6 1 / a n 1 p 6 0 / a n 0 p 5 7 / i n t 3 p 5 6 / p w m p 5 5 / c n t r 1 p 5 4 / c n t r 0 p 5 2 / s c l k 2 p 5 1 / s o u t 2 p 5 0 / s i n 2 p 4 6 / s c l k 1 p 4 5 / t x d 1 p 4 4 / r x d 1 p 4 3 / i n t 2 p 4 2 / i n t 1 c n v s s p 4 0 / i n t 4 0 / x c o u t x i n x o u t v s s r e s e t p 3 0 / d a 1 p 3 1 / d a 2 p 3 4 / r x d 3 p 3 5 / t x d 3 p 0 0 / a n 8 p 2 0 ( l e d 0 ) p 5 3 / s r d y 2 p 6 5 / a n 5 p 4 1 / i n t 0 0 / x c i n p 0 1 / a n 9 p 0 2 / a n 1 0 p 0 3 / a n 1 1 p 0 4 / a n 1 2 p 0 5 / a n 1 3 p 0 6 / a n 1 4 p 0 7 / a n 1 5 p 1 0 / i n t 4 1 p 1 1 / i n t 0 1 p 1 2 p 1 3 p 1 4 p 1 5 p 1 6 p 1 7 p 2 1 ( l e d 1 ) p 2 2 ( l e d 2 ) p 2 3 ( l e d 3 ) p 2 4 ( l e d 4 ) p 2 5 ( l e d 5 ) p 2 6 ( l e d 6 ) p 2 7 ( l e d 7 ) p 3 2 / s d a p 3 3 / s c l p 3 6 / s c l k 3 p 3 7 / s r d y 3 p 4 7 / s r d y 1 / c n t r 2 m 3 8 0 4 7 m 8 - x x x s p v p p : f l a s h m e m o r y v e r s i o n
4 3803/3804 group single-chip 8-bit cmos microcomputer mitsubishi microcomputers functional block diagram (package: 64p4b) fig. 5 3803 group functional block diagram functional block i n t 4 0 i n t 0 0 i n t 2 x i n o u t x r a m r o m c p u a x y s p c h p c l p s s s v 3 2 r e s e t 2 7 c c v 1 2 6 c n v s s c n t r 0 p 0 ( 8 ) 4 9 5 0 5 1 5 2 5 3 5 4 5 5 5 6 p 1 ( 8 ) 4 1 4 3 4 5 4 7 4 2 4 4 4 6 4 8 p 2 ( 8 ) 3 3 3 5 3 7 3 9 3 4 3 6 3 8 4 0 p 3 ( 8 ) 5 7 5 9 6 1 6 3 5 8 6 0 6 2 6 4 p 4 ( 8 ) 2 0 2 2 2 4 2 8 2 1 2 3 2 5 2 9 4 6 8 1 0 5 7 9 1 1 2 3 p 6 ( 8 ) i / o p o r t p 4 i / o p o r t p 0 i / o p o r t p 1 i / o p o r t p 2 ( l e d d r i v e ) i / o p o r t p 3 i / o p o r t p 6 c l o c k g e n e r a t i n g c i r c u i t c l o c k i n p u t p r e s c a l e r 1 2 ( 8 ) t i m e r 1 ( 8 ) d a t a b u s c n t r 1 t i m e r z ( 1 6 ) a - d c o n v e r t e r ( 1 0 ) v r e f a v s s i n t 3 1 2 1 4 1 6 1 8 1 3 1 5 1 7 1 9 i / o p o r t p 5 p w m ( 8 ) p 5 ( 8 ) s i / o 2 ( 8 ) s i / o 1 ( 8 ) d - a c o n v e r t e r 1 ( 8 ) x c i n c o u t x 3 0 3 1 2 8 2 9 c n t r 2 s i / o 3 ( 8 ) i n t 0 1 i n t 4 1 i n t 1 c l o c k o u t p u t s u b - cl o c k i n p u t s u b - cl o c k o u t p u t r e s e t i n p u t t i m e r 2 ( 8 ) t i m e r x ( 8 ) t i m e r y ( 8 ) p r e s c a l e r x ( 8 ) p r e s c a l e r y ( 8 ) d - a c o n v e r t e r 2 ( 8 )
5 3803/3804 group single-chip 8-bit cmos microcomputer mitsubishi microcomputers functional block diagram (package: 64p4b) fig. 6 3804 group functional block diagram i n t 4 0 i n t 0 0 i n t 2 x i n o u t x r a m r o m c p u a x y s p c h p c l p s s s v 3 2 r e s e t 2 7 c c v 1 2 6 c n v s s c n t r 0 p 0 ( 8 ) 4 9 5 0 5 1 5 2 5 3 5 4 5 5 5 6 p 1 ( 8 ) 4 1 4 3 4 5 4 7 4 2 4 4 4 6 4 8 p 2 ( 8 ) 3 3 3 5 3 7 3 9 3 4 3 6 3 8 4 0 p 3 ( 8 ) 5 7 5 9 6 1 6 3 5 8 6 0 6 2 6 4 p 4 ( 8 ) 2 0 2 2 2 4 2 8 2 1 2 3 2 5 2 9 4 6 8 1 0 5 7 9 1 1 2 3 p 6 ( 8 ) i / o p o r t p 4 i / o p o r t p 0 i / o p o r t p 1 i / o p o r t p 2 ( l e d d r i v e ) i / o p o r t p 3 i / o p o r t p 6 c l o c k g e n e r a t i n g c i r c u i t c l o c k i n p u t p r e s c a l e r 1 2 ( 8 ) t i m e r 1 ( 8 ) d a t a b u s c n t r 1 t i m e r z ( 1 6 ) a - d c o n v e r t e r ( 1 0 ) v r e f a v s s i n t 3 1 2 1 4 1 6 1 8 1 3 1 5 1 7 1 9 i / o p o r t p 5 p w m ( 8 ) p 5 ( 8 ) s i / o 2 ( 8 ) s i / o 1 ( 8 ) d - a c o n v e r t e r 1 ( 8 ) x c i n c o u t x 3 0 3 1 2 8 2 9 c n t r 2 s i / o 3 ( 8 ) i n t 0 1 i n t 4 1 i n t 1 c l o c k o u t p u t s u b - cl o c k i n p u t s u b - cl o c k o u t p u t r e s e t i n p u t t i m e r 2 ( 8 ) t i m e r x ( 8 ) t i m e r y ( 8 ) p r e s c a l e r x ( 8 ) p r e s c a l e r y ( 8 ) d - a c o n v e r t e r 2 ( 8 ) i 2 c
6 3803/3804 group single-chip 8-bit cmos microcomputer mitsubishi microcomputers v cc , v ss pin description functions name pin ?apply voltage of 2.7 v C 5.5 v to vcc, and 0 v to vss. ?in the flash memory version, apply voltage of 4.0 v C 5.5 v to vcc, and 0 v to vss ?this pin controls the operation mode of the chip. ?normally connected to v ss . ?in the flash memory version, this becomes v pp power source input pin. ?reference voltage input pin for a-d and d-a converters. ?analog power source input pin for a-d and d-a converters. ?connect to v ss . ?reset input pin for active l. ?input and output pins for the clock generating circuit. ?connect a ceramic resonator or quartz-crystal oscillator between the x in and x out pins to set the oscillation frequency. ?when an external clock is used, connect the clock source to the x in pin and leave the x out pin open. ?8-bit cmos i/o port. ?i/o direction register allows each pin to be individually programmed as either input or output. ?cmos compatible input level. ?cmos 3-state output structure. ?pull-up contol is enabled in a bit unit. ?p2 0 Cp2 7 are enabled to output large current for led drive. ?8-bit cmos i/o port. ?i/o direction register allows each pin to be individually programmed as either input or output. ?p3 0 , p3 1 , p3 4 Cp3 7 are cmos 3-state output structure. ?p3 2 , p3 3 are n-channel open-drain output structure. ?pull-up contol of p3 0 , p3 1 , p3 4 Cp3 7 is enabled in a bit unit. power source table 1 pin description (3803 group) function except a port function ?a-d converter input pin reference voltage analog power source clock input clock output i/o port p0 i/o port p1 i/o port p2 v ref av ss cnv ss input cnv ss reset reset input x in x out p0 0 /an 8 C p0 7 /an 15 p1 0 /int 01 p1 1 /int 41 p1 2 Cp1 7 p2 0 Cp2 7 p3 0 /da 1 p3 1 /da 2 p3 2 , p3 3 p3 4 /rxd 3 p3 5 /txd 3 p3 6 /s clk3 p3 7 /s rdy3 p4 0 /int 40 / x cout p4 1 /int 00 / x cin i/o port p3 ?interrupt input pin ?d-a converter input pin ?serial i/o3 function pin i/o port p4 ?8-bit cmos i/o port. ?i/o direction register allows each pin to be individually programmed as either input or output. ?cmos compatible input level. ?cmos 3-state output structure. ?pull-up contol is enabled in a bit unit. ?8-bit cmos i/o port. ?i/o direction register allows each pin to be individually programmed as either input or output. ?cmos compatible input level. ?cmos 3-state output structure. ?pull-up contol is enabled in a bit unit. ?interrupt input pin ?sub-clock generating i/o pin (resonater connected) p4 2 /int 1 p4 3 /int 2 p4 4 /rxd 1 p4 5 /txd 1 p4 6 /s clk1 p4 7 /s rdy1 /cntr 2 p5 0 /s in2 p5 1 /s out2 p5 2 /s clk2 p5 3 /s rdy2 p5 4 /cntr 0 p5 5 /cntr 1 p5 6 /pwm p5 7 /int 3 p6 0 /an 0 C p6 7 /an 7 ?interrupt input pin ?serial i/o1 function pin ?serial i/o1, timer z function pin i/o port p5 i/o port p6 ?serial i/o2 function pin ?timer x function pin ?timer y function pin ?pwm output pin ?interrupt input pin ?a-d converter input pin
7 3803/3804 group single-chip 8-bit cmos microcomputer mitsubishi microcomputers v cc , v ss functions name pin ?apply voltage of 2.7 v C 5.5 v to vcc, and 0 v to vss. ?in the flash memory version, apply voltage of 4.0 v C 5.5 v to vcc, and 0 v to vss ?this pin controls the operation mode of the chip. ?normally connected to v ss . ?in the flash memory version, this becomes v pp power source input pin. ?reference voltage input pin for a-d and d-a converters. ?analog power source input pin for a-d and d-a converters. ?connect to v ss . ?reset input pin for active l. ?input and output pins for the clock generating circuit. ?connect a ceramic resonator or quartz-crystal oscillator between the x in and x out pins to set the oscillation frequency. ?when an external clock is used, connect the clock source to the x in pin and leave the x out pin open. ?8-bit cmos i/o port. ?i/o direction register allows each pin to be individually programmed as either input or output. ?cmos compatible input level. ?cmos 3-state output structure. ?pull-up contol is enabled in a bit unit. ?p2 0 Cp2 7 are enabled to output large current for led drive. ?8-bit cmos i/o port. ?i/o direction register allows each pin to be individually programmed as either input or output. ?p3 2 to p3 3 can be switched between cmos compat- ible input level or smbus input level in the i 2 c-bus interface function. ?p3 0 , p3 1 , p3 4 Cp3 7 are cmos 3-state output structure. ?p3 2 , p3 3 are n-channel open-drain output structure. ?pull-up contol of p3 0 , p3 1 , p3 4 Cp3 7 is enabled in a bit unit. power source table 2 pin description (3804 group) function except a port function ?a-d converter input pin reference voltage analog power source clock input clock output i/o port p0 i/o port p1 i/o port p2 v ref av ss cnv ss input cnv ss reset reset input x in x out p0 0 /an 8 C p0 7 /an 15 p1 0 /int 01 p1 1 /int 41 p1 2 Cp1 7 p2 0 Cp2 7 p3 0 /da 1 p3 1 /da 2 p3 2 /sda p3 3 /scl p3 4 /rxd 3 p3 5 /txd 3 p3 6 /s clk3 p3 7 /s rdy3 i/o port p3 ?interrupt input pin ?d-a converter input pin ?serial i/o3 function pin i/o port p4 ?8-bit cmos i/o port. ?i/o direction register allows each pin to be individually programmed as either input or output. ?cmos compatible input level. ?cmos 3-state output structure. ?pull-up contol is enabled in a bit unit. ?8-bit cmos i/o port. ?i/o direction register allows each pin to be individually programmed as either input or output. ?cmos compatible input level. ?cmos 3-state output structure. ?pull-up contol is enabled in a bit unit. ?interrupt input pin ?sub-clock generating i/o pin (resonater connected) p4 0 /int 40 / x cout p4 1 /int 00 / x cin p4 2 /int 1 p4 3 /int 2 p4 4 /rxd 1 p4 5 /txd 1 p4 6 /s clk1 p4 7 /s rdy1 /cntr 2 p5 0 /s in2 p5 1 /s out2 p5 2 /s clk2 p5 3 /s rdy2 p5 4 /cntr 0 p5 5 /cntr 1 p5 6 /pwm p5 7 /int 3 p6 0 /an 0 C p6 7 /an 7 ?interrupt input pin ?serial i/o1 function pin ?serial i/o1, timer z function pin i/o port p5 i/o port p6 ?serial i/o2 function pin ?timer x function pin ?timer y function pin ?pwm output pin ?interrupt input pin ?a-d converter input pin ?i 2 c-bus interface function pins
8 3803/3804 group single-chip 8-bit cmos microcomputer mitsubishi microcomputers part numbering fig. 7 part numbering m 3 8 0 37 m 8 x x xs p p r o d u c t n a m e p a c k a g e t y p e s p : 6 4 p 4 b f p : 6 4 p 6 n - a h p : 6 4 p 6 q - a r o m n u m b e r o m i t t e d i n t h e f l a s h m e m o r y v e r s i o n . r o m s i z e 1 2 3 4 5 6 7 8 : 4 0 9 6 b y t e s : 8 1 9 2 b y t e s : 1 2 2 8 8 b y t e s : 1 6 3 8 4 b y t e s : 2 0 4 8 0 b y t e s : 2 4 5 7 6 b y t e s : 2 8 6 7 2 b y t e s : 3 2 7 6 8 b y t e s t h e f i r s t 1 2 8 b y t e s a n d t h e l a s t 2 b y t e s o f r o m a r e r e s e r v e d a r e a s ; t h e y c a n n o t b e u s e d a s a u s e r s r o m a r e a . h o w e v e r , t h e y c a n b e p r o g r a m m e d o r e r a s e d i n t h e f l a s h m e m o r y v e r s i o n , s o t h a t t h e u s e r s c a n u s e t h e m . m e m o r y t y p e m: m a s k r o m v e r s i o n f: f l a s h m e m o r y v e r s i o n r a m s i z e 0 1 2 3 4 : 1 9 2 b y t e s : 2 5 6 b y t e s : 3 8 4 b y t e s : 5 1 2 b y t e s : 6 4 0 b y t e s : s t a n d a r d o m i t t e d i n t h e f l a s h m e m o r y v e r s i o n . : 3 6 8 6 4 b y t e s : 4 0 9 6 0 b y t e s : 4 5 0 5 6 b y t e s : 4 9 1 5 2 b y t e s : 5 3 2 4 8 b y t e s : 5 7 3 4 4 b y t e s : 6 1 4 4 0 b y t e s 9 a b c d e f 5 6 7 8 9 : 7 6 8 b y t e s : 8 9 6 b y t e s : 1 0 2 4 b y t e s : 1 5 3 6 b y t e s : 2 0 4 8 b y t e s g r o u p 3 8 0 3 : 3 8 0 3 g r o u p 3 8 0 4 : 3 8 0 4 g r o u p
9 3803/3804 group single-chip 8-bit cmos microcomputer mitsubishi microcomputers group expansion mitsubishi plans to expand the 3803/3804 group as follows. memory type support for mask rom and flash memory versions. memory size flash memory size ......................................................... 60 k bytes mask rom size ................................................. 16 k to 32 k bytes ram size ............................................................ 640 to 2048 bytes packages 64p4b ......................................... 64-pin shrink plastic-molded dip 64p6n-a .................................... 0.8 mm-pitch plastic molded qfp 64p6q-a .................................. 0.5 mm-pitch plastic molded lqfp fig. 8 memory expansion plan memory expansion plan 4 8 k 3 2 k 2 8 k 2 4 k 2 0 k 1 6 k 1 2 k 8 k 3 8 45 1 26 4 07 6 88 9 61 0 2 4 6 0 k 1 1 5 21 2 8 01 4 0 81 5 3 6 r o m e x t e r a n a l 2 0 4 83 0 7 24 0 3 2 r o m s i z e ( b y t e s ) r a m s i z e ( b y t e s ) u n d e r d e v e l o p m e n t m 3 8 0 3 9 m f / f f m 3 8 0 4 9 m f / f f m 3 8 0 3 7 m 8 m 3 8 0 4 7 m 8 m 3 8 0 3 7 m 6 m 3 8 0 4 7 m 6 m 3 8 0 3 4 m 4 m 3 8 0 4 4 m 4 u n d e r d e v e l o p m e n t u n d e r d e v e l o p m e n t u n d e r d e v e l o p m e n t p r o d u c t s u n d e r d e v e l o p m e n t o r p l a n n i n g : t h e d e v e l o p m e n t s c h e d u l e a n d s p e c i f i c a t i o n m a y b e r e v i s e d w i t h o u t n o t i c e . t h e d e v e l o p m e n t o f pl a n n i n g p r o d u c t s m a y b e s t o p p e d . m 3 8 0 3 9 m c m 3 8 0 4 9 m c u n d e r d e v e l o p m e n t
10 3803/3804 group single-chip 8-bit cmos microcomputer mitsubishi microcomputers currently planning products are listed below. ram size (bytes) remarks package table 3 support products product name as of aug. 1999 32768 (32638) rom size (bytes) rom size for user in ( ) m38034m4-xxxsp m38034m4-xxxfp m38034m4-xxxhp m38044m4-xxxsp m38044m4-xxxfp m38044m4-xxxhp m38037m6-xxxsp m38037m6-xxxfp m38037m6-xxxhp m38047m6-xxxsp M38047M6-XXXFP m38047m6-xxxhp m38037m8-xxxsp m38037m8-xxxfp m38037m8-xxxhp m38047m8-xxxsp m38047m8-xxxfp m38047m8-xxxhp m38039mc-xxxsp m38039mc-xxxfp m38039mc-xxxhp m38049mc-xxxsp m38049mc-xxxfp m38049mc-xxxhp m38039mf-xxxsp m38039mf-xxxfp m38039mf-xxxhp m38049mf-xxxsp m38049mf-xxxfp m38049mf-xxxhp m38039ffsp m38039fffp m38039ffhp m38049ffsp m38049fffp m38049ffhp 1024 64p4b 64p6n-a 64p6q-a 64p4b 64p6n-a 64p6q-a 64p4b 64p6n-a 64p6q-a 64p4b 64p6n-a 64p6q-a 64p4b 64p6n-a 64p6q-a 64p4b 64p6n-a 64p6q-a 64p4b 64p6n-a 64p6q-a 64p4b 64p6n-a 64p6q-a 64p4b 64p6n-a 64p6q-a 64p4b 64p6n-a 64p6q-a 64p4b 64p6n-a 64p6q-a 64p4b 64p6n-a 64p6q-a mask rom version 49152 (49022) 61440 (61310) 61440 16384 (16254) 640 mask rom version 24576 (24446) 1024 2048 2048 2048 mask rom version mask rom version mask rom version flash memory version
11 3803/3804 group single-chip 8-bit cmos microcomputer mitsubishi microcomputers functional description central processing unit (cpu) the 3803/3804 group uses the standard 740 family instruction set. refer to the table of 740 family addressing modes and ma- chine instructions or the 740 family software manual for details on the instruction set. machine-resident 740 family instructions are as follows: the fst and slw instructions cannot be used. the stp, wit, mul, and div instructions can be used. [cpu mode register (cpum)] 003b 16 the cpu mode register contains the stack page selection bit, etc. the cpu mode register is allocated at address 003b 16 . fig.9 structure of cpu mode register c p u m o d e r e g i s t e r ( c p u m : a d d r e s s 0 0 3 b 1 6 ) b 7 b 0 r e s e r v e d ( d o n o t w r i t e 0 t o t h i s b i t w h e n u s i n g x c i n x c o u t o s c i l l a t i n g f u n c t i o n . ) s t a c k p a g e s e l e c t i o n b i t 0 : 0 p a g e 1 : 1 p a g e p r o c e s s o r m o d e b i t s b 1 b 0 0 0 : s i n g l e - c h i p m o d e 0 1 : 1 0 : n o t a v a i l a b l e 1 1 : p o r t x c s w i t c h b i t 0 : i / o p o r t f u n c t i o n ( s t o p o s c i l l a t i n g ) 1 : x c i n x c o u t o s c i l l a t i n g f u n c t i o n m a i n c l o c k ( x i n x o u t ) s t o p b i t 0 : o s c i l l a t i n g 1 : s t o p p e d m a i n c l o c k d i v i s i o n r a t i o s e l e c t i o n b i t s b 7 b 6 0 0 : f = f ( x i n ) / 2 ( h i g h - s p e e d m o d e ) 0 1 : f = f ( x i n ) / 8 ( m i d d l e - s p e e d m o d e ) 1 0 : f = f ( x c i n ) / 2 ( l o w - s p e e d m o d e ) 1 1 : n o t a v a i l a b l e
12 3803/3804 group single-chip 8-bit cmos microcomputer mitsubishi microcomputers misrg (1) bit 0 of address 0010 16: oscillation stabilizing time set af- ter stp instruction released bit when the mcu stops the clock oscillation by the stp instruction and the stp instruction has been released by an external interrupt source, usually, the fixed values of timer 1 and prescaler 12 (timer 1 = 01 16 , prescaler 12 = ff 16 ) are automatically reloaded in order for the oscillation to stabilize. the user can inhibit the au- tomatic setting by setting 1 to bit 0 of misrg (address 0010 16 ). however, by setting this bit to 1, the previous values, set just be- fore the stp instruction was executed, will remain in timer 1 and prescaler 12. therefore, you will need to set an appropriate value to each register, in accordance with the oscillation stabilizing time, before executing the stp instruction. figure 10 shows the structure of misrg. (2) bits 1, 2, 3 of address 0010 16: middle-speed mode auto- matic switch function in order to switch the clock mode of an mcu which has a sub- clock, the following procedure is necessary: set cpu mode register (003b 16 ) --> start main clock oscillation --> wait for oscillation stabilization --> switch to middle-speed mode (or high-speed mode). however, the 3803/3804 group has the built-in function which au- tomatically switches from low to middle-speed mode either by the scl/sda interrupt (only for the 3804 group) or by program. l middle-speed mode automatic switch by scl/sda interrupt (only for 3804 group) the scl/sda interrupt source enables an automatic switch when the middle-speed mode automatic switch set bit (bit 1) of misrg (address 0010 16 ) is set to 1. the conditions for an automatic switch execution depend on the settings of bits 5 and 6 of the i 2 c start/stop condition control register (address 0016 16 ). bit 5 is the scl/sda interrupt pin polarity selection bit and bit 6 is the scl/ sda interrupt pin selection bit. the main clock oscillation stabiliz- ing time can also be selected by middle-speed mode automatic switch wait time set bit (bit 2) of the misrg. l middle-speed mode automatic switch by program(for 3804/ 3803 group) the middle-speed mode can also be automatically switched by program while operating in low-speed mode. by setting the middle-speed automatic switch start bit (bit 3) of misrg (address 0010 16 ) to 1 in the condition that the middle-speed mode auto- matic switch set bit is 1 while operating in low-speed mode, the mcu will automatically switch to middle-speed mode. in this case, the oscillation stabilizing time of the main clock can be selected by the middle-speed automatic switch wait time set bit (bit 2) of misrg (address 0010 16 ). fig.10 structure of misrg m i s r g ( m i s r g : a d d r e s s 0 0 1 0 1 6 ) o s c i l l a t i o n s t a b i l i z i n g t i m e s e t a f t e r s t p i n s t r u c t i o n r e l e a s e d b i t m i d d l e - s p e e d m o d e a u t o m a t i c s w i t c h s e t b i t m i d d l e - s p e e d m o d e a u t o m a t i c s w i t c h w a i t t i m e s e t b i t m i d d l e - s p e e d m o d e a u t o m a t i c s w i t c h s t a r t b i t ( d e p e n d i n g o n p r o g r a m ) n o t u s e d ( r e t u r n 0 w h e n r e a d ) ( d o n o t w r i t e 1 t o t h i s b i t ) b 7 b 0 0 : a u t o m a t i c a l l y s e t ? 1 1 6 t o t i m e r 1 , f f 1 6 t o p r e s c a l e r 1 2 1 : a u t o m a t i c a l l y s e t d i s a b l e d 0 : n o t s e t a u t o m a t i c a l l y 1 : a u t o m a t i c s w i t c h i n g e n a b l e d ( n o t e s 1 , 2 ) 0 : 4 . 5 t o 5 . 5 m a c h i n e c y c l e s 1 : 6 . 5 t o 7 . 5 m a c h i n e c y c l e s 0 : i n v a l i d 1 : a u t o m a t i c s w i t c h s t a r t ( n o t e 2 ) n o t e s1: d u r i n g o p e r a t i o n i n l o w - s p e e d m o d e , i t i s p o s s i b l e a u t o m a t i c a l l y t o s w i t c h t o m i d d l e - s p e e d m o d e o w i n g t o s c l / s d a i n t e r r u p t . t h i s i s v a l i d o n l y f o r t h e 3 8 0 4 g r o u p . 2 : w h e n a u t o m a t i c s w i t c h t o m i d d l e - s p e e d m o d e f r o m l o w - s p e e d m o d e o c c u r s , t h e v a l u e s o f c p u m o d e r e g i s t e r ( 3 b 1 6 ) c h a n g e .
13 3803/3804 group single-chip 8-bit cmos microcomputer mitsubishi microcomputers memory special function register (sfr) area the special function register area in the zero page contains con- trol registers such as i/o ports and timers. ram ram is used for data storage and for stack area of subroutine calls and interrupts. rom the first 128 bytes and the last 2 bytes of rom are reserved for device testing and the rest is a user area for storing programs. interrupt vector area the interrupt vector area contains reset and interrupt vectors. zero page access to this area with only 2 bytes is possible in the zero page addressing mode. special page access to this area with only 2 bytes is possible in the special page addressing mode. fig. 11 memory map diagram 0100 16 0000 16 0040 16 ff00 16 ffdc 16 fffe 16 ffff 16 192 256 384 512 640 768 896 1024 1536 2048 xxxx 16 00ff 16 013f 16 01bf 16 023f 16 02bf 16 033f 16 03bf 16 043f 16 063f 16 083f 16 4096 8192 12288 16384 20480 24576 28672 32768 36864 40960 45056 49152 53248 57344 61440 f000 16 e000 16 d000 16 c000 16 b000 16 a000 16 9000 16 8000 16 7000 16 6000 16 5000 16 4000 16 3000 16 2000 16 1000 16 f080 16 e080 16 d080 16 c080 16 b080 16 a080 16 9080 16 8080 16 7080 16 6080 16 5080 16 4080 16 3080 16 2080 16 1080 16 yyyy 16 zzzz 16 ram rom 0ff0 16 0fff 16 sfr area not used interrupt vector area rom area reserved rom area (128 bytes) zero page special page ram area ram size (bytes) address xxxx 16 rom size (bytes) address yyyy 16 reserved rom area address zzzz 16 sfr area not used
14 3803/3804 group single-chip 8-bit cmos microcomputer mitsubishi microcomputers fig. 12 memory map of 3803 groups special function register (sfr) 0 0 2 0 1 6 0 0 2 1 1 6 0 0 2 2 1 6 0 0 2 3 1 6 0 0 2 4 1 6 0 0 2 5 1 6 0 0 2 6 1 6 0 0 2 7 1 6 0 0 2 8 1 6 0 0 2 9 1 6 0 0 2 a 1 6 0 0 2 b 1 6 0 0 2 c 1 6 0 0 2 d 1 6 0 0 2 e 1 6 0 0 2 f 1 6 0 0 3 0 1 6 0 0 3 1 1 6 0 0 3 2 1 6 0 0 3 3 1 6 0 0 3 4 1 6 0 0 3 5 1 6 0 0 3 6 1 6 0 0 3 7 1 6 0 0 3 8 1 6 0 0 3 9 1 6 0 0 3 a 1 6 0 0 3 b 1 6 0 0 3 c 1 6 0 0 3 d 1 6 0 0 3 e 1 6 0 0 3 f 1 6 0 0 0 0 1 6 0 0 0 1 1 6 0 0 0 2 1 6 0 0 0 3 1 6 0 0 0 4 1 6 0 0 0 5 1 6 0 0 0 6 1 6 0 0 0 7 1 6 0 0 0 8 1 6 0 0 0 9 1 6 0 0 0 a 1 6 0 0 0 b 1 6 0 0 0 c 1 6 0 0 0 d 1 6 0 0 0 e 1 6 0 0 0 f 1 6 0 0 1 0 1 6 0 0 1 1 1 6 0 0 1 2 1 6 0 0 1 3 1 6 0 0 1 4 1 6 0 0 1 5 1 6 0 0 1 6 1 6 0 0 1 7 1 6 0 0 1 8 1 6 0 0 1 9 1 6 0 0 1 a 1 6 0 0 1 b 1 6 0 0 1 c 1 6 0 0 1 d 1 6 0 0 1 e 1 6 0 0 1 f 1 6 s e r i a l i / o 2 r e g i s t e r ( s i o 2 ) p o r t p 0 ( p 0 ) p o r t p 0 d i r e c t i o n r e g i s t e r ( p 0 d ) p o r t p 1 ( p 1 ) p o r t p 1 d i r e c t i o n r e g i s t e r ( p 1 d ) p o r t p 2 ( p 2 ) p o r t p 2 d i r e c t i o n r e g i s t e r ( p 2 d ) p o r t p 3 ( p 3 ) p o r t p 3 d i r e c t i o n r e g i s t e r ( p 3 d ) p o r t p 4 ( p 4 ) p o r t p 4 d i r e c t i o n r e g i s t e r ( p 4 d ) p o r t p 5 ( p 5 ) p o r t p 5 d i r e c t i o n r e g i s t e r ( p 5 d ) p o r t p 6 ( p 6 ) p o r t p 6 d i r e c t i o n r e g i s t e r ( p 6 d ) t i m e r 1 2 , x c o u n t s o u r c e s e l e c t i o n r e g i s t e r ( t 1 2 x c s s ) t i m e r y, z c o u n t s o u r c e s e l e c t i o n r e g i s t e r ( t y z c s s ) m i s r g t r a n s m i t / r e c e i v e b u f f e r r e g i s t e r 1 ( t b 1 / r b 1 ) s e r i a l i / o 1 s t a t u s r e g i s t e r ( s i o 1 s t s ) s e r i a l i / o 1 c o n t r o l r e g i s t e r ( s i o 1 c o n ) u a r t 1 c o n t r o l r e g i s t e r ( u a r t 1 c o n ) b a u d r a t e g e n e r a t o r ( b r g 1 ) s e r i a l i / o 2 c o n t r o l r e g i s t e r ( s i o 2 c o n ) i n t e r r u p t c o n t r o l r e g i s t e r 2 ( i c o n 2 ) a - d c o n v e r s i o n r e g i s t e r 1 ( a d 1 ) p r e s c a l e r y ( p r e y ) t i m e r y ( t y ) a d / d a c o n t r o l r e g i s t e r ( a d c o n ) d - a 1 c o n v e r s i o n r e g i s t e r ( d a 1 ) d - a 2 c o n v e r s i o n r e g i s t e r ( d a 2 ) i n t e r r u p t e d g e s e l e c t i o n r e g i s t e r ( i n t e d g e ) c p u m o d e r e g i s t e r ( c p u m ) i n t e r r u p t r e q u e s t r e g i s t e r 1 ( i r e q 1 ) i n t e r r u p t r e q u e s t r e g i s t e r 2 ( i r e q 2 ) i n t e r r u p t c o n t r o l r e g i s t e r 1 ( i c o n 1 ) p r e s c a l e r 1 2 ( p r e 1 2 ) t i m e r 2 ( t 2 ) p r e s c a l e r x ( p r e x ) t i m e r x ( t x ) t i m e r 1 ( t 1 ) t i m e r x y m o d e r e g i s t e r ( t m ) a - d c o n v e r s i o n r e g i s t e r 2 ( a d 2 ) i n t e r r u p t s o u r c e s e l e c t i o n r e g i s t e r ( i n t s e l ) w a t c h d o g t i m e r c o n t r o l r e g i s t e r ( w d t c o n ) 0 f f 0 1 6 0 f f 1 1 6 p o r t p 0 p u l l - u p c o n t r o l r e g i s t e r ( p u l l 0 ) t i m e r z l o w - o r d e r ( t z l ) t i m e r z h i g h - o r d e r ( t z h ) p w m c o n t r o l r e g i s t e r ( p w m c o n ) p w m p r e s c a l e r ( p r e p w m ) t i m e r z m o d e r e g i s t e r ( t z m ) p w m r e g i s t e r ( p w m ) b a u d r a t e g e n e r a t o r 3 ( b r g 3 ) t r a n s m i t / r e c e i v e b u f f e r r e g i s t e r 3 ( t b 3 / r b 3 ) s e r i a l i / o 3 s t a t u s r e g i s t e r ( s i o 3 s t s ) s e r i a l i / o 3 c o n t r o l r e g i s t e r ( s i o 3 c o n ) u a r t 3 c o n t r o l r e g i s t e r ( u a r t 3 c o n ) 0 f f e 1 6 0 f f f 1 6 f l a s h c o m m a n d r e g i s t e r ( f c m d ) f l a s h m e m o r y c o n t r o l r e g i s t e r ( f c o n ) p o r t p 1 p u l l - u p c o n t r o l r e g i s t e r ( p u l l 1 ) 0 f f 2 1 6 0 f f 3 1 6 p o r t p 2 p u l l - u p c o n t r o l r e g i s t e r ( p u l l 2 ) p o r t p 3 p u l l - u p c o n t r o l r e g i s t e r ( p u l l 3 ) 0 f f 4 1 6 p o r t p 4 p u l l - u p c o n t r o l r e g i s t e r ( p u l l 4 ) 0 f f 5 1 6 0 f f 6 1 6 p o r t p 5 p u l l - u p c o n t r o l r e g i s t e r ( p u l l 5 ) p o r t p 6 p u l l - u p c o n t r o l r e g i s t e r ( p u l l 6 ) r e s e r v e d ] r e s e r v e d ] r e s e r v e d ] r e s e r v e d ] r e s e r v e d ] r e s e r v e d ] r e s e r v e d ] ] r e s e r v e d a r e a : d o n o t w r i t e a n y d a t a t o t h i s a d d r e s s e s , b e c a u s e t h e s e a r e a s a r e r e s e r v e d .
15 3803/3804 group single-chip 8-bit cmos microcomputer mitsubishi microcomputers 0 f f 7 1 6 0 0 2 0 1 6 0 0 2 1 1 6 0 0 2 2 1 6 0 0 2 3 1 6 0 0 2 4 1 6 0 0 2 5 1 6 0 0 2 6 1 6 0 0 2 7 1 6 0 0 2 8 1 6 0 0 2 9 1 6 0 0 2 a 1 6 0 0 2 b 1 6 0 0 2 c 1 6 0 0 2 d 1 6 0 0 2 e 1 6 0 0 2 f 1 6 0 0 3 0 1 6 0 0 3 1 1 6 0 0 3 2 1 6 0 0 3 3 1 6 0 0 3 4 1 6 0 0 3 5 1 6 0 0 3 6 1 6 0 0 3 7 1 6 0 0 3 8 1 6 0 0 3 9 1 6 0 0 3 a 1 6 0 0 3 b 1 6 0 0 3 c 1 6 0 0 3 d 1 6 0 0 3 e 1 6 0 0 3 f 1 6 0 0 0 0 1 6 0 0 0 1 1 6 0 0 0 2 1 6 0 0 0 3 1 6 0 0 0 4 1 6 0 0 0 5 1 6 0 0 0 6 1 6 0 0 0 7 1 6 0 0 0 8 1 6 0 0 0 9 1 6 0 0 0 a 1 6 0 0 0 b 1 6 0 0 0 c 1 6 0 0 0 d 1 6 0 0 0 e 1 6 0 0 0 f 1 6 0 0 1 0 1 6 0 0 1 1 1 6 0 0 1 2 1 6 0 0 1 3 1 6 0 0 1 4 1 6 0 0 1 5 1 6 0 0 1 6 1 6 0 0 1 7 1 6 0 0 1 8 1 6 0 0 1 9 1 6 0 0 1 a 1 6 0 0 1 b 1 6 0 0 1 c 1 6 0 0 1 d 1 6 0 0 1 e 1 6 0 0 1 f 1 6 s e r i a l i / o 2 r e g i s t e r ( s i o 2 ) p o r t p 0 ( p 0 ) p o r t p 0 d i r e c t i o n r e g i s t e r ( p 0 d ) p o r t p 1 ( p 1 ) p o r t p 1 d i r e c t i o n r e g i s t e r ( p 1 d ) p o r t p 2 ( p 2 ) p o r t p 2 d i r e c t i o n r e g i s t e r ( p 2 d ) p o r t p 3 ( p 3 ) p o r t p 3 d i r e c t i o n r e g i s t e r ( p 3 d ) p o r t p 4 ( p 4 ) p o r t p 4 d i r e c t i o n r e g i s t e r ( p 4 d ) p o r t p 5 ( p 5 ) p o r t p 5 d i r e c t i o n r e g i s t e r ( p 5 d ) p o r t p 6 ( p 6 ) p o r t p 6 d i r e c t i o n r e g i s t e r ( p 6 d ) t i m e r 1 2 , x c o u n t s o u r c e s e l e c t i o n r e g i s t e r ( t 1 2 x c s s ) t i m e r y, z c o u n t s o u r c e s e l e c t i o n r e g i s t e r ( t y z c s s ) m i s r g t r a n s m i t / r e c e i v e b u f f e r r e g i s t e r 1 ( t b 1 / r b 1 ) s e r i a l i / o 1 s t a t u s r e g i s t e r ( s i o 1 s t s ) s e r i a l i / o 1 c o n t r o l r e g i s t e r ( s i o 1 c o n ) u a r t 1 c o n t r o l r e g i s t e r ( u a r t 1 c o n ) b a u d r a t e g e n e r a t o r ( b r g 1 ) s e r i a l i / o 2 c o n t r o l r e g i s t e r ( s i o 2 c o n ) i n t e r r u p t c o n t r o l r e g i s t e r 2 ( i c o n 2 ) a - d c o n v e r s i o n r e g i s t e r 1 ( a d 1 ) p r e s c a l e r y ( p r e y ) t i m e r y ( t y ) a d / d a c o n t r o l r e g i s t e r ( a d c o n ) d - a 1 c o n v e r s i o n r e g i s t e r ( d a 1 ) d - a 2 c o n v e r s i o n r e g i s t e r ( d a 2 ) i n t e r r u p t e d g e s e l e c t i o n r e g i s t e r ( i n t e d g e ) c p u m o d e r e g i s t e r ( c p u m ) i n t e r r u p t r e q u e s t r e g i s t e r 1 ( i r e q 1 ) i n t e r r u p t r e q u e s t r e g i s t e r 2 ( i r e q 2 ) i n t e r r u p t c o n t r o l r e g i s t e r 1 ( i c o n 1 ) p r e s c a l e r 1 2 ( p r e 1 2 ) t i m e r 2 ( t 2 ) p r e s c a l e r x ( p r e x ) t i m e r x ( t x ) t i m e r 1 ( t 1 ) t i m e r x y m o d e r e g i s t e r ( t m ) i 2 c d a t a s h i f t r e g i s t e r ( s 0 ) i 2 c s l a v e a d d r e s s r e g i s t e r 0 ( s 0 d 0 ) i 2 c s t a t u s r e g i s t e r ( s 1 ) i 2 c c o n t r o l r e g i s t e r ( s 1 d ) i 2 c c l o c k c o n t r o l r e g i s t e r ( s 2 ) i 2 c s t a r t / s t o p c o n d i t i o n c o n t r o l r e g i s t e r ( s 2 d ) a - d c o n v e r s i o n r e g i s t e r 2 ( a d 2 ) i n t e r r u p t s o u r c e s e l e c t i o n r e g i s t e r ( i n t s e l ) w a t c h d o g t i m e r c o n t r o l r e g i s t e r ( w d t c o n ) 0 f f 0 1 6 0 f f 1 1 6 p o r t p 0 p u l l - u p c o n t r o l r e g i s t e r ( p u l l 0 ) i 2 c s p e c i a l m o d e s t a t u s r e g i s t e r ( s 3 ) i 2 c s p e c i a l m o d e c o n t r o l r e g i s t e r ( s 3 d ) 0 f f 8 1 6 i 2 c s l a v e a d d r e s s r e g i s t e r 1 ( s 0 d 1 ) 0 f f 9 1 6 i 2 c s l a v e a d d r e s s r e g i s t e r 2 ( s 0 d 2 ) t i m e r z l o w - o r d e r ( t z l ) t i m e r z h i g h - o r d e r ( t z h ) p w m c o n t r o l r e g i s t e r ( p w m c o n ) p w m p r e s c a l e r ( p r e p w m ) t i m e r z m o d e r e g i s t e r ( t z m ) p w m r e g i s t e r ( p w m ) b a u d r a t e g e n e r a t o r 3 ( b r g 3 ) t r a n s m i t / r e c e i v e b u f f e r r e g i s t e r 3 ( t b 3 / r b 3 ) s e r i a l i / o 3 s t a t u s r e g i s t e r ( s i o 3 s t s ) s e r i a l i / o 3 c o n t r o l r e g i s t e r ( s i o 3 c o n ) u a r t 3 c o n t r o l r e g i s t e r ( u a r t 3 c o n ) 0 f f e 1 6 0 f f f 1 6 f l a s h c o m m a n d r e g i s t e r ( f c m d ) f l a s h m e m o r y c o n t r o l r e g i s t e r ( f c o n ) p o r t p 1 p u l l - u p c o n t r o l r e g i s t e r ( p u l l 1 ) 0 f f 2 1 6 0 f f 3 1 6 p o r t p 2 p u l l - u p c o n t r o l r e g i s t e r ( p u l l 2 ) p o r t p 3 p u l l - u p c o n t r o l r e g i s t e r ( p u l l 3 ) 0 f f 4 1 6 p o r t p 4 p u l l - u p c o n t r o l r e g i s t e r ( p u l l 4 ) 0 f f 5 1 6 0 f f 6 1 6 p o r t p 5 p u l l - u p c o n t r o l r e g i s t e r ( p u l l 5 ) p o r t p 6 p u l l - u p c o n t r o l r e g i s t e r ( p u l l 6 ) fig. 13 memory map of 3804 groups special function register (sfr)
16 3803/3804 group single-chip 8-bit cmos microcomputer mitsubishi microcomputers i/o ports the i/o ports have direction registers which determine the input/ output direction of each individual pin. each bit in a direction reg- ister corresponds to one pin, and each pin can be set to be input port or output port. when 0 is written to the bit corresponding to a pin, that pin be- p0 0 /an 8 Cp0 7 /an 15 p1 0 /int 41 p1 1 /int 01 p1 2 Cp1 7 p2 0 /led 0 C p2 7 /led 7 p3 0 /da 1 p3 1 /da 2 p3 2 p3 3 p3 4 /rxd 3 p3 5 /txd 3 p3 6 /s clk3 p3 7 /s rdy3 p4 0 /int 00 /x cin p4 1 /int 40 /x cout p4 2 /int 1 p4 3 /int 2 p4 4 /rxd 1 p4 5 /txd 1 p4 6 /s clk1 p4 7 /s rdy1 /cntr 2 pin name i/o structure cmos compatible input level cmos 3-state output non-port function ref.no. table 4 i/o port function of 3803 group related sfrs port p0 port p1 port p3 (1) (2) port p2 a-d converter input external interrupt input d-a converter output ad/da control register interrupt edge selection register ad/da control register (3) (4) (5) cmos compatible input level cmos 3-state output cmos compatible input level n-channel open-drain output cmos compatible input level cmos 3-state output port p4 serial i/o3 function i/o serial i/o3 control register uart3 control register (6) (7) (8) (9) external interrupt input sub-clock generating circuit external interrupt input serial i/o1 function i/o interrupt edge selection register cpu mode register interrupt edge selection register serial i/o1 control register uart1 control register (10) (11) (2) (6) (7) (8) (12) serial i/o1 function i/o timer z function i/o serial i/o1 control register timer z mode register serial i/o2 control register serial i/o2 function i/o port p5 port p6 (13) (14) (15) (16) (17) (18) (2) (1) timer x, y function i/o pwm output external interrupt input a-d converter input timer xy mode register pwm control register interrupt edge selection register ad/da control register notes 1 : refer to the applicable sections how to use double-function ports as function i/o ports, . 2 : make sure that the input level at each pin is either 0 v or v cc during execution of the stp instruction. when an input level is at an intermediate potential, a current will flow from v cc to v ss through the input-stage gate. comes an input pin. when 1 is written to that bit, that pin be- comes an output pin. if data is read from a pin which is set to output, the value of the port output latch is read, not the value of the pin itself. pins set to input are floating. if a pin set to input is written to, only the port output latch is written to and the pin remains floating. p5 0 /s in2 p5 1 /s out2 p5 2 /s clk2 p5 3 /s rdy2 p5 4 /cntr 0 p5 5 /cntr 1 p5 6 /pwm p5 7 /int 3 p6 0 /an 0 Cp6 7 /an 7 cmos compatible input level cmos 3-state output cmos compatible input level cmos 3-state output cmos compatible input level cmos 3-state output
17 3803/3804 group single-chip 8-bit cmos microcomputer mitsubishi microcomputers p0 0 /an 8 Cp0 7 /an 15 p1 0 /int 41 p1 1 /int 01 p1 2 Cp1 7 p2 0 /led 0 C p2 7 /led 7 p3 0 /da 1 p3 1 /da 2 p3 2 /sda p3 3 /scl pin name i/o structure cmos compatible input level cmos 3-state output non-port function ref.no. table 5 i/o port function of 3804 group related sfrs port p0 port p1 port p3 (1) (2) port p2 a-d converter input external interrupt input d-a converter output ad/da control register interrupt edge selection register ad/da control register (3) (4) i 2 c-bus interface func- tion i/o i 2 c control register (5) cmos compatible input level cmos 3-state output cmos compatible input level n-channel open-drain output cmos/smbus input level (when selecting i 2 c-bus interface function) cmos compatible input level cmos 3-state output p3 4 /rxd 3 p3 5 /txd 3 p3 6 /s clk3 p3 7 /s rdy3 p4 0 /int 00 /x cin p4 1 /int 40 /x cout p4 2 /int 1 p4 3 /int 2 p4 4 /rxd 1 p4 5 /txd 1 p4 6 /s clk1 p4 7 /s rdy1 /cntr 2 port p4 serial i/o3 function i/o serial i/o3 control register uart3 control register (6) (7) (8) (9) cmos compatible input level cmos 3-state output external interrupt input sub-clock generating circuit external interrupt input interrupt edge selection register cpu mode register interrupt edge selection register serial i/o1 control register uart1 control register (10) (11) (2) (6) (7) (8) (12) serial i/o1 function i/o serial i/o1 function i/o timer z function i/o serial i/o1 control register timer z mode register serial i/o2 control register serial i/o2 function i/o p5 0 /s in2 p5 1 /s out2 p5 2 /s clk2 p5 3 /s rdy2 p5 4 /cntr 0 p5 5 /cntr 1 p5 6 /pwm p5 7 /int 3 p6 0 /an 0 Cp6 7 /an 7 port p5 port p6 cmos compatible input level cmos 3-state output (13) (14) (15) (16) (17) (18) (2) (1) timer x, y function i/o pwm output external interrupt input a-d converter input timer xy mode register pwm control register interrupt edge selection register ad/da control register cmos compatible input level cmos 3-state output notes 1 : refer to the applicable sections how to use double-function ports as function i/o ports, . 2 : make sure that the input level at each pin is either 0 v or v cc during execution of the stp instruction. when an input level is at an intermediate potential, a current will flow from v cc to v ss through the input-stage gate.
18 3803/3804 group single-chip 8-bit cmos microcomputer mitsubishi microcomputers fig. 14 port block diagram of 3803 group (1) ( 6 ) p o r t s p 3 4 , p 4 4 s e r i a l i / o i n p u t ( 1 ) p o r t s p 0 , p 6 a - d c o n v e r t e r i n p u t a n a l o g i n p u t p i n s e l e c t i o n b i t d i r e c t i o n r e g i s t e r d a t a b u s p o r t l a t c h p u l l - u p c o n t r o l b i t ( 2 ) p o r t s p 1 0 , p 1 1 , p 4 2 , p 4 3 , p 5 7 i n t e r r u p t i n p u t ( 3 ) p o r t s p 1 2 t o p 1 7 , p 2 ( 4 ) p o r t s p 3 0 , p 3 1 d a 1 o u t p u t e n a b l e ( p 3 0 ) d a 2 o u t p u t e n a b l e ( p 3 1 ) ( 8 ) p o r t s p 3 6 , p 4 6 ( 7 ) p o r t s p 3 5 , p 4 5 ( 5 ) p o r t s p 3 2 , p 3 3 d a t a b u s d i r e c t i o n r e g i s t e r p o r t l a t c h p u l l - u p c o n t r o l b i t p u l l - u p c o n t r o l b i t d i r e c t i o n r e g i s t e r p o r t l a t c h d a t a b u s d a t a b u s d i r e c t i o n r e g i s t e r p o r t l a t c h p u l l - u p c o n t r o l b i t d - a c o n v e r t e r o u t p u t d a t a b u s d i r e c t i o n r e g i s t e r p o r t l a t c h p u l l - u p c o n t r o l b i t s e r i a l i / o e n a b l e b i t r e c e i v e e n a b l e b i t d i r e c t i o n r e g i s t e r p o r t l a t c h d a t a b u s d i r e c t i o n r e g i s t e r p o r t l a t c h d a t a b u s p u l l - u p c o n t r o l b i t s e r i a l i / o e n a b l e b i t t r a n s m i t e n a b l e b i t p - c h a n n e l o u t p u t d i s a b l e b i t s e r i a l i / o e n a b l e b i t s e r i a l i / o m o d e s e l e c t i o n b i t s e r i a l i / o e n a b l e b i t s e r i a l i / o s y n c h r o n o u s c l o c k s e l e c t i o n b i t d a t a b u s d i r e c t i o n r e g i s t e r p o r t l a t c h p u l l - u p c o n t r o l b i t s e r i a l i / o e x t e r n a l c l o c k i n p u t s e r i a l i / o c l o c k o u t p u t s e r i a l i / o o u t p u t
19 3803/3804 group single-chip 8-bit cmos microcomputer mitsubishi microcomputers ( 1 0 ) p o r t p 4 0 ( 1 1 ) p o r t p 4 1 ( 1 3 ) p o r t p 5 0 p o r t x c s w i t c h b i t i n t 4 0 i n t e r r u p t i n p u t p o r t p 4 1 s e r i a l i / o 2 i n p u t ( 1 2 ) p o r t p 4 7 c n t r 2 i n t e r r u p t i n p u t ( 9 ) p o r t p 3 7 s r d y 3 o u t p u t e n a b l e b i t ( 1 4 ) p o r t p 5 1 i n t 0 0 i n t e r r u p t i n p u t s e r i a l i / o 3 e n a b l e b i t s e r i a l i / o 3 m o d e s e l e c t i o n b i t d a t a b u s d i r e c t i o n r e g i s t e r p o r t l a t c h p u l l - u p c o n t r o l b i t s e r i a l i / o 3 r e a d y o u t p u t p u l l - u p c o n t r o l b i t d a t a b u s d i r e c t i o n r e g i s t e r p o r t l a t c h p o r t x c s w i t c h b i t o s c i l l a t o r s r d y 1 o u t p u t e n a b l e b i t s e r i a l i / o 1 e n a b l e b i t s e r i a l i / o 1 m o d e s e l e c t i o n b i t d a t a b u s d i r e c t i o n r e g i s t e r p o r t l a t c h p u l l - u p c o n t r o l b i t s e r i a l i / o 1 r e a d y o u t p u t p u l s e o u t p u t m o d e t i m e r o u t p u t d a t a b u s d i r e c t i o n r e g i s t e r p o r t l a t c h p u l l - u p c o n t r o l b i t s u b - c l o c k g e n e r a t i n g c i r c u i t i n p u t p o r t x c s w i t c h b i t p u l l - u p c o n t r o l b i t d a t a b u s d i r e c t i o n r e g i s t e r p o r t l a t c h p u l l - u p c o n t r o l b i t d a t a b u s d i r e c t i o n r e g i s t e r p o r t l a t c h s e r i a l i / o 2 o u t p u t s e r i a l i / o 2 t r a n s m i t c o m p l e t i o n s i g n a l s e r i a l i / o 2 p o r t s e l e c t i o n b i t p - c h a n n e l o u t p u t d i s a b l e b i t fig. 15 port block diagram of 3803 group (2)
20 3803/3804 group single-chip 8-bit cmos microcomputer mitsubishi microcomputers ( 1 6 ) p o r t p 5 3 ( 1 5 ) p o r t p 5 2 ( 1 7 ) p o r t s p 5 4 , p 5 5 ( 1 8 ) p o r t p 5 6 p w m o u t p u t s e r i a l i / o 2 s y n c h r o n o u s c l o c k s e l e c t i o n b i t s e r i a l i / o 2 p o r t s e l e c t i o n b i t d a t a b u s d i r e c t i o n r e g i s t e r p o r t l a t c h p u l l - u p c o n t r o l b i t s e r i a l i / o 2 e x t e r n a l c l o c k i n p u t s e r i a l i / o 2 c l o c k o u t p u t s r d y 2 e n a b l e b i t s e r i a l i / o 2 r e a d y o u t p u t d a t a b u s d i r e c t i o n r e g i s t e r p o r t l a t c h d a t a b u s d i r e c t i o n r e g i s t e r p o r t l a t c h p u l l - u p c o n t r o l b i t c n t r i n t e r r u p t i n p u t p u l s e o u t p u t m o d e t i m e r o u t p u t d a t a b u s d i r e c t i o n r e g i s t e r p o r t l a t c h p w m o u t p u t e n a b l e b i t p u l l - u p c o n t r o l b i t p u l l - u p c o n t r o l b i t fig. 16 port block diagram of 3803 group (3)
21 3803/3804 group single-chip 8-bit cmos microcomputer mitsubishi microcomputers fig. 17 port block diagram of 3804 group (1) ( 6 ) p o r t s p 3 4 , p 4 4 s e r i a l i / o i n p u t ( 1 ) p o r t s p 0 , p 6 a - d c o n v e r t e r i n p u t a n a l o g i n p u t p i n s e l e c t i o n b i t d i r e c t i o n r e g i s t e r d a t a b u s p o r t l a t c h p u l l - u p c o n t r o l b i t ( 2 ) p o r t s p 1 0 , p 1 1 , p 4 2 , p 4 3 , p 5 7 i n t e r r u p t i n p u t ( 3 ) p o r t s p 1 2 t o p 1 7 , p 2 ( 4 ) p o r t s p 3 0 , p 3 1 d a 1 o u t p u t e n a b l e ( p 3 0 ) d a 2 o u t p u t e n a b l e ( p 3 1 ) ( 8 ) p o r t s p 3 6 , p 4 6 ( 7 ) p o r t s p 3 5 , p 4 5 ( 5 ) p o r t s p 3 2 , p 3 3 d a t a b u s d i r e c t i o n r e g i s t e r p o r t l a t c h p u l l - u p c o n t r o l b i t p u l l - u p c o n t r o l b i t d i r e c t i o n r e g i s t e r p o r t l a t c h d a t a b u s d a t a b u s d i r e c t i o n r e g i s t e r p o r t l a t c h p u l l - u p c o n t r o l b i t d - a c o n v e r t e r o u t p u t d a t a b u s d i r e c t i o n r e g i s t e r p o r t l a t c h p u l l - u p c o n t r o l b i t s e r i a l i / o e n a b l e b i t r e c e i v e e n a b l e b i t d i r e c t i o n r e g i s t e r p o r t l a t c h d a t a b u s d i r e c t i o n r e g i s t e r p o r t l a t c h d a t a b u s p u l l - u p c o n t r o l b i t s e r i a l i / o e n a b l e b i t t r a n s m i t e n a b l e b i t p - c h a n n e l o u t p u t d i s a b l e b i t s e r i a l i / o e n a b l e b i t s e r i a l i / o m o d e s e l e c t i o n b i t s e r i a l i / o e n a b l e b i t s e r i a l i / o s y n c h r o n o u s c l o c k s e l e c t i o n b i t d a t a b u s d i r e c t i o n r e g i s t e r p o r t l a t c h p u l l - u p c o n t r o l b i t s e r i a l i / o e x t e r n a l c l o c k i n p u t s e r i a l i / o c l o c k o u t p u t s d a o u t p u t s c l o u t p u t s d a i n p u t s c l i n p u t i 2 c - b u s i n t e r f a c e e n a b l e b i t s e r i a l i / o o u t p u t
22 3803/3804 group single-chip 8-bit cmos microcomputer mitsubishi microcomputers ( 1 0 ) p o r t p 4 0 ( 1 1 ) p o r t p 4 1 ( 1 3 ) p o r t p 5 0 p o r t x c s w i t c h b i t i n t 4 0 i n t e r r u p t i n p u t p o r t p 4 1 s e r i a l i / o 2 i n p u t ( 1 2 ) p o r t p 4 7 c n t r 2 i n t e r r u p t i n p u t ( 9 ) p o r t p 3 7 s r d y 3 o u t p u t e n a b l e b i t ( 1 4 ) p o r t p 5 1 i n t 0 0 i n t e r r u p t i n p u t s e r i a l i / o 3 e n a b l e b i t s e r i a l i / o 3 m o d e s e l e c t i o n b i t d a t a b u s d i r e c t i o n r e g i s t e r p o r t l a t c h p u l l - u p c o n t r o l b i t s e r i a l i / o 3 r e a d y o u t p u t p u l l - u p c o n t r o l b i t d a t a b u s d i r e c t i o n r e g i s t e r p o r t l a t c h p o r t x c s w i t c h b i t o s c i l l a t o r s r d y 1 o u t p u t e n a b l e b i t s e r i a l i / o 1 e n a b l e b i t s e r i a l i / o 1 m o d e s e l e c t i o n b i t d a t a b u s d i r e c t i o n r e g i s t e r p o r t l a t c h p u l l - u p c o n t r o l b i t s e r i a l i / o 1 r e a d y o u t p u t p u l s e o u t p u t m o d e t i m e r o u t p u t d a t a b u s d i r e c t i o n r e g i s t e r p o r t l a t c h p u l l - u p c o n t r o l b i t s u b - c l o c k g e n e r a t i n g c i r c u i t i n p u t p o r t x c s w i t c h b i t p u l l - u p c o n t r o l b i t d a t a b u s d i r e c t i o n r e g i s t e r p o r t l a t c h p u l l - u p c o n t r o l b i t d a t a b u s d i r e c t i o n r e g i s t e r p o r t l a t c h s e r i a l i / o 2 o u t p u t s e r i a l i / o 2 t r a n s m i t c o m p l e t i o n s i g n a l s e r i a l i / o 2 p o r t s e l e c t i o n b i t p - c h a n n e l o u t p u t d i s a b l e b i t fig. 18 port block diagram of 3804 group (2)
23 3803/3804 group single-chip 8-bit cmos microcomputer mitsubishi microcomputers fig. 19 port block diagram of 3804 group (3) ( 1 6 ) p o r t p 5 3 ( 1 5 ) p o r t p 5 2 ( 1 7 ) p o r t s p 5 4 , p 5 5 ( 1 8 ) p o r t p 5 6 p w m o u t p u t s e r i a l i / o 2 s y n c h r o n o u s c l o c k s e l e c t i o n b i t s e r i a l i / o 2 p o r t s e l e c t i o n b i t d a t a b u s d i r e c t i o n r e g i s t e r p o r t l a t c h p u l l - u p c o n t r o l b i t s e r i a l i / o 2 e x t e r n a l c l o c k i n p u t s e r i a l i / o 2 c l o c k o u t p u t s r d y 2 o u t p u t e n a b l e b i t s e r i a l i / o 2 r e a d y o u t p u t d a t a b u s d i r e c t i o n r e g i s t e r p o r t l a t c h d a t a b u s d i r e c t i o n r e g i s t e r p o r t l a t c h p u l l - u p c o n t r o l b i t c n t r i n t e r r u p t i n p u t p u l s e o u t p u t m o d e t i m e r o u t p u t d a t a b u s d i r e c t i o n r e g i s t e r p o r t l a t c h p w m o u t p u t e n a b l e b i t p u l l - u p c o n t r o l b i t p u l l - u p c o n t r o l b i t
24 3803/3804 group single-chip 8-bit cmos microcomputer mitsubishi microcomputers p o r t p 0 p u l l - u p c o n t r o l r e g i s t e r b 7b 0 p 0 0 p u l l - u p c o n t r o l b i t 0 : n o p u l l - u p 1 : p u l l - u p p 0 1 p u l l - u p c o n t r o l b i t 0 : n o p u l l - u p 1 : p u l l - u p p 0 2 p u l l - u p c o n t r o l b i t 0 : n o p u l l - u p 1 : p u l l - u p p 0 3 p u l l - u p c o n t r o l b i t 0 : n o p u l l - u p 1 : p u l l - u p p 0 4 p u l l - u p c o n t r o l b i t 0 : n o p u l l - u p 1 : p u l l - u p p 0 5 p u l l - u p c o n t r o l b i t 0 : n o p u l l - u p 1 : p u l l - u p p 0 6 p u l l - u p c o n t r o l b i t 0 : n o p u l l - u p 1 : p u l l - u p p 0 7 p u l l - u p c o n t r o l b i t 0 : n o p u l l - u p 1 : p u l l - u p b 7b 0 p o r t p 1 p u l l - u p c o n t r o l r e g i s t e r p 1 0 p u l l - u p c o n t r o l b i t 0 : n o p u l l - u p 1 : p u l l - u p p 1 1 p u l l - u p c o n t r o l b i t 0 : n o p u l l - u p 1 : p u l l - u p p 1 2 p u l l - u p c o n t r o l b i t 0 : n o p u l l - u p 1 : p u l l - u p p 1 3 p u l l - u p c o n t r o l b i t 0 : n o p u l l - u p 1 : p u l l - u p p 1 4 p u l l - u p c o n t r o l b i t 0 : n o p u l l - u p 1 : p u l l - u p p 1 5 p u l l - u p c o n t r o l b i t 0 : n o p u l l - u p 1 : p u l l - u p p 1 6 p u l l - u p c o n t r o l b i t 0 : n o p u l l - u p 1 : p u l l - u p p 1 7 p u l l - u p c o n t r o l b i t 0 : n o p u l l - u p 1 : p u l l - u p ( p u l l 1 : a d d r e s s 0 f f 1 1 6 ) ( p u l l 0 : a d d r e s s 0 f f 0 1 6 ) n o t e : p u l l - u p c o n t r o l i s v a l i d w h e n t h e c o r r e s p o n d i n g b i t o f t h e p o r t d i r e c t i o n r e g i s t e r i s 0 ( i n p u t ) . w h e n t h a t b i t i s 1 ( o u t p u t ) , p u l l - u p c a n n o t b e s e t t o t h e p o r t o f w h i c h p u l l - u p i s s e l e c t e d . n o t e : p u l l - u p c o n t r o l i s v a l i d w h e n t h e c o r r e s p o n d i n g b i t o f t h e p o r t d i r e c t i o n r e g i s t e r i s 0 ( i n p u t ) . w h e n t h a t b i t i s 1 ( o u t p u t ) , p u l l - u p c a n n o t b e s e t t o t h e p o r t o f w h i c h p u l l - u p i s s e l e c t e d . fig. 20 structure of port pull-up control register (1)
25 3803/3804 group single-chip 8-bit cmos microcomputer mitsubishi microcomputers p o r t p 2 p u l l - u p c o n t r o l r e g i s t e r b 7b 0 p 2 0 p u l l - u p c o n t r o l b i t 0 : n o p u l l - u p 1 : p u l l - u p p 2 1 p u l l - u p c o n t r o l b i t 0 : n o p u l l - u p 1 : p u l l - u p p 2 2 p u l l - u p c o n t r o l b i t 0 : n o p u l l - u p 1 : p u l l - u p p 2 3 p u l l - u p c o n t r o l b i t 0 : n o p u l l - u p 1 : p u l l - u p p 2 4 p u l l - u p c o n t r o l b i t 0 : n o p u l l - u p 1 : p u l l - u p p 2 5 p u l l - u p c o n t r o l b i t 0 : n o p u l l - u p 1 : p u l l - u p p 2 6 p u l l - u p c o n t r o l b i t 0 : n o p u l l - u p 1 : p u l l - u p p 2 7 p u l l - u p c o n t r o l b i t 0 : n o p u l l - u p 1 : p u l l - u p b 7b 0 p o r t p 3 p u l l - u p c o n t r o l r e g i s t e r p 3 0 p u l l - u p c o n t r o l b i t 0 : n o p u l l - u p 1 : p u l l - u p p 3 1 p u l l - u p c o n t r o l b i t 0 : n o p u l l - u p 1 : p u l l - u p n o t u s e d ( r e t u r n 0 w h e n r e a d ) p 3 4 p u l l - u p c o n t r o l b i t 0 : n o p u l l - u p 1 : p u l l - u p p 3 5 p u l l - u p c o n t r o l b i t 0 : n o p u l l - u p 1 : p u l l - u p p 3 6 p u l l - u p c o n t r o l b i t 0 : n o p u l l - u p 1 : p u l l - u p p 3 7 p u l l - u p c o n t r o l b i t 0 : n o p u l l - u p 1 : p u l l - u p ( p u l l 3 : a d d r e s s 0 f f 3 1 6 ) ( p u l l 2 : a d d r e s s 0 f f 2 1 6 ) n o t e : p u l l - u p c o n t r o l i s v a l i d w h e n t h e c o r r e s p o n d i n g b i t o f t h e p o r t d i r e c t i o n r e g i s t e r i s 0 ( i n p u t ) . w h e n t h a t b i t i s 1 ( o u t p u t ) , p u l l - u p c a n n o t b e s e t t o t h e p o r t o f w h i c h p u l l - u p i s s e l e c t e d . n o t e : p u l l - u p c o n t r o l i s v a l i d w h e n t h e c o r r e s p o n d i n g b i t o f t h e p o r t d i r e c t i o n r e g i s t e r i s 0 ( i n p u t ) . w h e n t h a t b i t i s 1 ( o u t p u t ) , p u l l - u p c a n n o t b e s e t t o t h e p o r t o f w h i c h p u l l - u p i s s e l e c t e d . fig. 21 structure of port pull-up control register (2)
26 3803/3804 group single-chip 8-bit cmos microcomputer mitsubishi microcomputers p o r t p 4 p u l l - u p c o n t r o l r e g i s t e r b 7b 0 p 4 0 p u l l - u p c o n t r o l b i t 0 : n o p u l l - u p 1 : p u l l - u p p 4 1 p u l l - u p c o n t r o l b i t 0 : n o p u l l - u p 1 : p u l l - u p p 4 2 p u l l - u p c o n t r o l b i t 0 : n o p u l l - u p 1 : p u l l - u p p 4 3 p u l l - u p c o n t r o l b i t 0 : n o p u l l - u p 1 : p u l l - u p p 4 4 p u l l - u p c o n t r o l b i t 0 : n o p u l l - u p 1 : p u l l - u p p 4 5 p u l l - u p c o n t r o l b i t 0 : n o p u l l - u p 1 : p u l l - u p p 4 6 p u l l - u p c o n t r o l b i t 0 : n o p u l l - u p 1 : p u l l - u p p 4 7 p u l l - u p c o n t r o l b i t 0 : n o p u l l - u p 1 : p u l l - u p b 7b 0 p o r t p 5 p u l l - u p c o n t r o l r e g i s t e r p 5 0 p u l l - u p c o n t r o l b i t 0 : n o p u l l - u p 1 : p u l l - u p p 5 1 p u l l - u p c o n t r o l b i t 0 : n o p u l l - u p 1 : p u l l - u p p 5 2 p u l l - u p c o n t r o l b i t 0 : n o p u l l - u p 1 : p u l l - u p p 5 3 p u l l - u p c o n t r o l b i t 0 : n o p u l l - u p 1 : p u l l - u p p 5 4 p u l l - u p c o n t r o l b i t 0 : n o p u l l - u p 1 : p u l l - u p p 5 5 p u l l - u p c o n t r o l b i t 0 : n o p u l l - u p 1 : p u l l - u p p 5 6 p u l l - u p c o n t r o l b i t 0 : n o p u l l - u p 1 : p u l l - u p p 5 7 p u l l - u p c o n t r o l b i t 0 : n o p u l l - u p 1 : p u l l - u p ( p u l l 5 : a d d r e s s 0 f f 5 1 6 ) ( p u l l 4 : a d d r e s s 0 f f 4 1 6 ) n o t e : p u l l - u p c o n t r o l i s v a l i d w h e n t h e c o r r e s p o n d i n g b i t o f t h e p o r t d i r e c t i o n r e g i s t e r i s 0 ( i n p u t ) . w h e n t h a t b i t i s 1 ( o u t p u t ) , p u l l - u p c a n n o t b e s e t t o t h e p o r t o f w h i c h p u l l - u p i s s e l e c t e d . n o t e : p u l l - u p c o n t r o l i s v a l i d w h e n t h e c o r r e s p o n d i n g b i t o f t h e p o r t d i r e c t i o n r e g i s t e r i s 0 ( i n p u t ) . w h e n t h a t b i t i s 1 ( o u t p u t ) , p u l l - u p c a n n o t b e s e t t o t h e p o r t o f w h i c h p u l l - u p i s s e l e c t e d . fig. 22 structure of port pull-up control register (3)
27 3803/3804 group single-chip 8-bit cmos microcomputer mitsubishi microcomputers fig. 23 structure of port pull-up control register (4) p o r t p 6 p u l l - u p c o n t r o l r e g i s t e r b 7b 0 p 6 0 p u l l - u p c o n t r o l b i t 0 : n o p u l l - u p 1 : p u l l - u p p 6 1 p u l l - u p c o n t r o l b i t 0 : n o p u l l - u p 1 : p u l l - u p p 6 2 p u l l - u p c o n t r o l b i t 0 : n o p u l l - u p 1 : p u l l - u p p 6 3 p u l l - u p c o n t r o l b i t 0 : n o p u l l - u p 1 : p u l l - u p p 6 4 p u l l - u p c o n t r o l b i t 0 : n o p u l l - u p 1 : p u l l - u p p 6 5 p u l l - u p c o n t r o l b i t 0 : n o p u l l - u p 1 : p u l l - u p p 6 6 p u l l - u p c o n t r o l b i t 0 : n o p u l l - u p 1 : p u l l - u p p 6 7 p u l l - u p c o n t r o l b i t 0 : n o p u l l - u p 1 : p u l l - u p ( p u l l 6 : a d d r e s s 0 f f 6 1 6 ) n o t e : p u l l - u p c o n t r o l i s v a l i d w h e n t h e c o r r e s p o n d i n g b i t o f t h e p o r t d i r e c t i o n r e g i s t e r i s 0 ( i n p u t ) . w h e n t h a t b i t i s 1 ( o u t p u t ) , p u l l - u p c a n n o t b e s e t t o t h e p o r t o f w h i c h p u l l - u p i s s e l e c t e d .
28 3803/3804 group single-chip 8-bit cmos microcomputer mitsubishi microcomputers interrupts the 3803 groups interrupts are a type of vector and occur by 16 sources among 21 sources: eight external, twelve internal, and one software. the 3804 groups interrupts occur by 16 sources among 23 sources: nine external, thirteen internal, and one software. interrupt control each interrupt is controlled by an interrupt request bit, an interrupt enable bit, and the interrupt disable flag except for the software in- terrupt set by the brk instruction. an interrupt occurs if the corresponding interrupt request and enable bits are 1 and the in- terrupt disable flag is 0. interrupt enable bits can be set or cleared by software. interrupt request bits can be cleared by software, but cannot be set by software. the reset and the brk instruction cannot be disabled with any flag or bit. the i (interrupt disable) flag disables all interrupts ex- cept the reset and the brk instruction interrupt. when several interrupt requests occur at the same time, the inter- rupts are received according to priority. interrupt operation by acceptance of an interrupt, the following operations are auto- matically performed: 1. the contents of the program counter and the processor status register are automatically pushed onto the stack. 2. the interrupt disable flag is set and the corresponding interrupt request bit is cleared. 3. the interrupt jump destination address is read from the vector table into the program counter. interrupt source selection which of each combination of the following interrupt sources can be selected by the interrupt source selection register (address 0039 16 ). 1. int 0 or timer z 2. serial i/o1 transmission or scl, sda (for 3804 group) 3. cntr 0 or scl, sda (for 3804 group) 4. cntr 1 or serial i/o3 reception (for 3804 group) 5. serial i/o2 or timer z 6. int 2 or i 2 c 7. int 4 or cntr 2 8. a-d converter or serial i/o3 transmission external interrupt pin selection the occurrence sources of the external interrupt int 0 and int 4 can be selected from either input from int 00 and int 40 pin, or in- put from int 01 and int 41 pin by the int 0 , int 4 interrupt switch bit of interrupt edge selection register (bit 6 of address 003a 16 ). n notes when setting of the following register or bit is changed, the inter- rupt request bit may be set to 1. ? interrupt edge selection register (address 003a 16 ) ? interrupt source selection register (address 0039 16 ) accept the interrupt after clearing the interrupt request bit to 0 af- ter interrupt is disabled and the above register or bit is set.
29 3803/3804 group single-chip 8-bit cmos microcomputer mitsubishi microcomputers interrupt request generating conditions remarks interrupt source low fffc 16 fffa 16 high fffd 16 fffb 16 priority 1 2 table 6 interrupt vector addresses and priority of 3803 group notes 1: vector addresses contain interrupt jump destination addresses. 2: reset function in the same way as an interrupt with the highest priority. vector addresses (note 1) reset (note 2) int 0 timer z int 1 serial i/o1 reception serial i/o1 transmission at reset at detection of either rising or falling edge of int 0 input at timer z underflow at detection of either rising or falling edge of int 1 input at completion of serial i/o1 data reception at completion of serial i/o1 transmission shift or when transmission buffer is empty at timer x underflow at timer y underflow at timer 1 underflow at timer 2 underflow at detection of either rising or falling edge of cntr 0 input at detection of either rising or falling edge of cntr 1 input at completion of serial i/o3 data reception at completion of serial i/o2 data transmission or reception at timer z underflow at detection of either rising or falling edge of int 2 input at detection of either rising or falling edge of int 3 input at detection of either rising or falling edge of int 4 input at detection of either rising or falling edge of cntr 2 input at completion of a-d conversion at completion of serial i/o3 transmission shift or when transmission buffer is empty at brk instruction execution non-maskable external interrupt (active edge selectable) external interrupt (active edge selectable) valid when serial i/o1 is selected valid when serial i/o1 is selected fff8 16 fff6 16 fff4 16 fff2 16 fff0 16 ffee 16 ffec 16 ffea 16 fff9 16 fff7 16 fff5 16 fff3 16 fff1 16 ffef 16 ffed 16 ffeb 16 3 4 5 6 7 8 9 10 timer x timer y timer 1 timer 2 cntr 0 cntr 1 serial i/o3 reception serial i/o2 timer z int 2 int 3 int 4 stp release timer underflow external interrupt (active edge selectable) external interrupt (active edge selectable) valid when serial i/o3 is selected valid when serial i/o2 is selected external interrupt (active edge selectable) external interrupt (active edge selectable) external interrupt (active edge selectable) external interrupt (active edge selectable) valid when serial i/o3 is selected non-maskable software interrupt 11 ffe9 16 ffe8 16 12 cntr 2 a-d converter serial i/o3 transmission brk instruction 14 15 13 16 17 ffe7 16 ffe5 16 ffe3 16 ffe1 16 ffdf 16 ffdd 16 ffe6 16 ffe4 16 ffe2 16 ffe0 16 ffde 16 ffdc 16
30 3803/3804 group single-chip 8-bit cmos microcomputer mitsubishi microcomputers interrupt request generating conditions remarks interrupt source low fffc 16 fffa 16 high fffd 16 fffb 16 priority 1 2 table 7 interrupt vector addresses and priority of 3804 group notes 1: vector addresses contain interrupt jump destination addresses. 2: reset function in the same way as an interrupt with the highest priority. vector addresses (note 1) reset (note 2) int 0 timer z int 1 serial i/o1 reception serial i/o1 transmission at reset at detection of either rising or falling edge of int 0 input at timer z underflow at detection of either rising or falling edge of int 1 input at completion of serial i/o1 data reception at completion of serial i/o1 transmission shift or when transmission buffer is empty at detection of either rising or falling edge of scl or sda at timer x underflow at timer y underflow at timer 1 underflow at timer 2 underflow at detection of either rising or falling edge of cntr 0 input at detection of either rising or falling edge of scl or sda at detection of either rising or falling edge of cntr 1 input at completion of serial i/o3 data reception at completion of serial i/o2 data transmission or reception at timer z underflow at detection of either rising or falling edge of int 2 input at completion of data transfer at detection of either rising or falling edge of int 3 input at detection of either rising or falling edge of int 4 input at detection of either rising or falling edge of cntr 2 input at completion of a-d conversion at completion of serial i/o3 transmission shift or when transmission buffer is empty at brk instruction execution non-maskable external interrupt (active edge selectable) external interrupt (active edge selectable) valid when serial i/o1 is selected valid when serial i/o1 is selected fff8 16 fff6 16 fff4 16 fff2 16 fff0 16 ffee 16 ffec 16 ffea 16 fff9 16 fff7 16 fff5 16 fff3 16 fff1 16 ffef 16 ffed 16 ffeb 16 3 4 5 6 7 8 9 10 external interrupt (active edge selectable) scl, sda timer x timer y timer 1 timer 2 cntr 0 scl, sda cntr 1 serial i/o3 reception serial i/o2 timer z int 2 stp release timer underflow external interrupt (active edge selectable) external interrupt (active edge selectable) external interrupt (active edge selectable) valid when serial i/o3 is selected valid when serial i/o2 is selected external interrupt (active edge selectable) external interrupt (active edge selectable) external interrupt (active edge selectable) external interrupt (active edge selectable) valid when serial i/o3 is selected non-maskable software interrupt 11 ffe9 16 ffe8 16 12 i 2 c int 3 int 4 cntr 2 a-d converter serial i/o3 transmission brk instruction 14 15 13 16 17 ffe7 16 ffe5 16 ffe3 16 ffe1 16 ffdf 16 ffdd 16 ffe6 16 ffe4 16 ffe2 16 ffe0 16 ffde 16 ffdc 16
31 3803/3804 group single-chip 8-bit cmos microcomputer mitsubishi microcomputers fig. 24 interrupt control i n t e r r u p t d i s a b l e f l a g ( i ) i n t e r r u p t r e q u e s t i n t e r r u p t r e q u e s t b i t i n t e r r u p t e n a b l e b i t b r k i n s t r u c t i o n r e s e t
32 3803/3804 group single-chip 8-bit cmos microcomputer mitsubishi microcomputers fig. 25 structure of interrupt-related registers of 3803 group i n t e r r u p t e d g e s e l e c t i o n r e g i s t e r i n t 0 a c t i v e e d g e s e l e c t i o n b i t i n t 1 a c t i v e e d g e s e l e c t i o n b i t n o t u s e d ( r e t u r n s 0 w h e n r e a d ) i n t 2 a c t i v e e d g e s e l e c t i o n b i t i n t 3 a c t i v e e d g e s e l e c t i o n b i t i n t 4 a c t i v e e d g e s e l e c t i o n b i t i n t 0 , i n t 4 i n t e r r u p t s w i t c h b i t 0 : i n t 0 0 , i n t 4 0 i n t e r r u p t 1 : i n t 0 1 , i n t 4 1 i n t e r r u p t n o t u s e d ( r e t u r n s 0 w h e n r e a d ) ( i n t e d g e : a d d r e s s 0 0 3 a 1 6 ) i n t e r r u p t r e q u e s t r e g i s t e r 1 i n t 0 / t i m e r z i n t e r r u p t r e q u e s t b i t i n t 1 i n t e r r u p t r e q u e s t b i t s e r i a l i / o 1 r e c e i v e i n t e r r u p t r e q u e s t b i t s e r i a l i / o 1 t r a n s m i t i n t e r r u p t r e q u e s t b i t t i m e r x i n t e r r u p t r e q u e s t b i t t i m e r y i n t e r r u p t r e q u e s t b i t t i m e r 1 i n t e r r u p t r e q u e s t b i t t i m e r 2 i n t e r r u p t r e q u e s t b i t i n t e r r u p t c o n t r o l r e g i s t e r 1 0 : n o i n t e r r u p t r e q u e s t i s s u e d 1 : i n t e r r u p t r e q u e s t i s s u e d ( i r e q 1 : a d d r e s s 0 0 3 c 1 6 ) ( i c o n 1 : a d d r e s s 0 0 3 e 1 6 ) i n t e r r u p t r e q u e s t r e g i s t e r 2 c n t r 0 i n t e r r u p t r e q u e s t b i t c n t r 1 / s e r i a l i / o 3 r e c e i v e i n t e r r u p t r e q u e s t b i t s e r i a l i / o 2 / t i m e r z i n t e r r u p t r e q u e s t b i t i n t 2 i n t e r r u p t r e q u e s t b i t i n t 3 i n t e r r u p t r e q u e s t b i t i n t 4 /c n t r 2 i n t e r r u p t r e q u e s t b i t a d c o n v e r t e r / s e r i a l i / o 3 t r a n s m i t i n t e r r u p t r e q u e s t b i t n o t u s e d ( r e t u r n s 0 w h e n r e a d ) ( i r e q 2 : a d d r e s s 0 0 3 d 1 6 ) i n t e r r u p t c o n t r o l r e g i s t e r 2 0 : i n t e r r u p t s d i s a b l e d 1 : i n t e r r u p t s e n a b l e d ( i c o n 2 : a d d r e s s 0 0 3 f 1 6 ) 0 : f a l l i n g e d g e a c t i v e 1 : r i s i n g e d g e a c t i v e 0 : f a l l i n g e d g e a c t i v e 1 : r i s i n g e d g e a c t i v e c n t r 0 i n t e r r u p t e n a b l e b i t c n t r 1 / s e r i a l i / o 3 r e c e i v e i n t e r r u p t e n a b l e b i t s e r i a l i / o 2 / t i m e r z i n t e r r u p t e n a b l e b i t i n t 2 i n t e r r u p t e n a b l e b i t i n t 3 i n t e r r u p t e n a b l e b i t i n t 4 /c n t r 2 i n t e r r u p t e n a b l e b i t a d c o n v e r t e r / s e r i a l i / o 3 t r a n s m i t i n t e r r u p t e n a b l e b i t n o t u s e d ( r e t u r n s 0 w h e n r e a d ) i n t 0 / t i m e r z i n t e r r u p t e n a b l e b i t i n t 1 i n t e r r u p t e n a b l e b i t s e r i a l i / o 1 r e c e i v e i n t e r r u p t e n a b l e b i t s e r i a l i / o 1 t r a n s m i t i n t e r r u p t e n a b l e b i t t i m e r x i n t e r r u p t e n a b l e b i t t i m e r y i n t e r r u p t e n a b l e b i t t i m e r 1 i n t e r r u p t e n a b l e b i t t i m e r 2 i n t e r r u p t e n a b l e b i t b 7 i n t 0 / t i m e r z i n t e r r u p t s o u r c e s e l e c t i o n b i t 0 : i n t 0 i n t e r r u p t 1 : t i m e r z i n t e r r u p t s e r i a l i / o 2 / t i m e r z i n t e r r u p t s o u r c e s e l e c t i o n b i t 0 : s e r i a l i / o 2 i n t e r r u p t 1 : t i m e r z i n t e r r u p t n o t u s e d (d o n o t w r i t e 1 t o t h e s e b i t s . ) i n t 4 / c n t r 2 i n t e r r u p t s o u r c e s e l e c t i o n b i t 0 : i n t 4 i n t e r r u p t 1 : c n t r 2 i n t e r r u p t n o t u s e d ( d o n o t w r i t e 1 t o t h i s b i t . ) c n t r 1 / s e r i a l i / o 3 r e c e i v e i n t e r r u p t s o u r c e s e l e c t i o n b i t 0 : c n t r 1 i n t e r r u p t 1 : s e r i a l i / o 3 r e c e i v e i n t e r r u p t a d c o n v e r t e r / s e r i a l i / o 3 t r a n s m i t i n t e r r u p t s o u r c e s e l e c t i o n b i t 0 : a - d c o n v e r t e r i n t e r r u p t 1 : s e r i a l i / o 3 t r a n s m i t i n t e r r u p t i n t e r r u p t s o u r c e s e l e c t i o n r e g i s t e r ( d o n o t w r i t e 1 t o t h e s e b i t s s i m u l t a n e o u s l y . ) ( i n t s e l : a d d r e s s 0 0 3 9 1 6 ) b 0 b 7 b 0 b 7 b 0 b 7 b 0 b 7 b 0 b 7 b 0
33 3803/3804 group single-chip 8-bit cmos microcomputer mitsubishi microcomputers fig. 26 structure of interrupt-related registers of 3804 group i n t e r r u p t e d g e s e l e c t i o n r e g i s t e r i n t 0 a c t i v e e d g e s e l e c t i o n b i t i n t 1 a c t i v e e d g e s e l e c t i o n b i t n o t u s e d ( r e t u r n s 0 w h e n r e a d ) i n t 2 a c t i v e e d g e s e l e c t i o n b i t i n t 3 a c t i v e e d g e s e l e c t i o n b i t i n t 4 a c t i v e e d g e s e l e c t i o n b i t i n t 0 , i n t 4 i n t e r r u p t s w i t c h b i t 0 : i n t 0 0 , i n t 4 0 i n t e r r u p t 1 : i n t 0 1 , i n t 4 1 i n t e r r u p t n o t u s e d ( r e t u r n s 0 w h e n r e a d ) ( i n t e d g e : a d d r e s s 0 0 3 a 1 6 ) i n t e r r u p t r e q u e s t r e g i s t e r 1 i n t 0 / t i m e r z i n t e r r u p t r e q u e s t b i t i n t 1 i n t e r r u p t r e q u e s t b i t s e r i a l i / o 1 r e c e i v e i n t e r r u p t r e q u e s t b i t s e r i a l i / o 1 t r a n s m i t / s c l , s d a i n t e r r u p t r e q u e s t b i t t i m e r x i n t e r r u p t r e q u e s t b i t t i m e r y i n t e r r u p t r e q u e s t b i t t i m e r 1 i n t e r r u p t r e q u e s t b i t t i m e r 2 i n t e r r u p t r e q u e s t b i t i n t e r r u p t c o n t r o l r e g i s t e r 1 0 : n o i n t e r r u p t r e q u e s t i s s u e d 1 : i n t e r r u p t r e q u e s t i s s u e d ( i r e q 1 : a d d r e s s 0 0 3 c 1 6 ) ( i c o n 1 : a d d r e s s 0 0 3 e 1 6 ) i n t e r r u p t r e q u e s t r e g i s t e r 2 c n t r 0 /s c l , s d a i n t e r r u p t r e q u e s t b i t c n t r 1 / s e r i a l i / o 3 r e c e i v e i n t e r r u p t r e q u e s t b i t s e r i a l i / o 2 / t i m e r z i n t e r r u p t r e q u e s t b i t i n t 2 / i 2 c i n t e r r u p t r e q u e s t b i t i n t 3 i n t e r r u p t r e q u e s t b i t i n t 4 /c n t r 2 i n t e r r u p t r e q u e s t b i t a d c o n v e r t e r / s e r i a l i / o 3 t r a n s m i t i n t e r r u p t r e q u e s t b i t n o t u s e d ( r e t u r n s 0 w h e n r e a d ) ( i r e q 2 : a d d r e s s 0 0 3 d 1 6 ) i n t e r r u p t c o n t r o l r e g i s t e r 2 0 : i n t e r r u p t s d i s a b l e d 1 : i n t e r r u p t s e n a b l e d ( i c o n 2 : a d d r e s s 0 0 3 f 1 6 ) 0 : f a l l i n g e d g e a c t i v e 1 : r i s i n g e d g e a c t i v e 0 : f a l l i n g e d g e a c t i v e 1 : r i s i n g e d g e a c t i v e c n t r 0 / s c l , s d a i n t e r r u p t e n a b l e b i t c n t r 1 / s e r i a l i / o 3 r e c e i v e i n t e r r u p t e n a b l e b i t s e r i a l i / o 2 / t i m e r z i n t e r r u p t e n a b l e b i t i n t 2 / i 2 c i n t e r r u p t e n a b l e b i t i n t 3 i n t e r r u p t e n a b l e b i t i n t 4 /c n t r 2 i n t e r r u p t e n a b l e b i t a d c o n v e r t e r / s e r i a l i / o 3 t r a n s m i t i n t e r r u p t e n a b l e b i t n o t u s e d ( r e t u r n s 0 w h e n r e a d ) i n t 0 / t i m e r z i n t e r r u p t e n a b l e b i t i n t 1 i n t e r r u p t e n a b l e b i t s e r i a l i / o 1 r e c e i v e i n t e r r u p t e n a b l e b i t s e r i a l i / o 1 t r a n s m i t / s c l , s d a i n t e r r u p t e n a b l e b i t t i m e r x i n t e r r u p t e n a b l e b i t t i m e r y i n t e r r u p t e n a b l e b i t t i m e r 1 i n t e r r u p t e n a b l e b i t t i m e r 2 i n t e r r u p t e n a b l e b i t b 7 i n t 0 / t i m e r z i n t e r r u p t s o u r c e s e l e c t i o n b i t 0 : i n t 0 i n t e r r u p t 1 : t i m e r z i n t e r r u p t s e r i a l i / o 2 / t i m e r z i n t e r r u p t s o u r c e s e l e c t i o n b i t 0 : s e r i a l i / o 2 i n t e r r u p t 1 : t i m e r z i n t e r r u p t s e r i a l i / o 1 t r a n s m i t / s c l , s d a i n t e r r u p t s o u r c e s e l e c t i o n b i t 0 : s e r i a l i / o 1 t r a n s m i t i n t e r r u p t 1 : s c l , s d a i n t e r r u p t c n t r 0 / s c l , s d a i n t e r r u p t s o u r c e s e l e c t i o n b i t 0 : c n t r 0 i n t e r r u p t 1 : s c l , s d a i n t e r r u p t i n t 4 / c n t r 2 i n t e r r u p t s o u r c e s e l e c t i o n b i t 0 : i n t 4 i n t e r r u p t 1 : c n t r 2 i n t e r r u p t i n t 2 / i 2 c i n t e r r u p t s o u r c e s e l e c t i o n b i t 0 : i n t 2 i n t e r r u p t 1 : i 2 c i n t e r r u p t c n t r 1 / s e r i a l i / o 3 r e c e i v e i n t e r r u p t s o u r c e s e l e c t i o n b i t 0 : c n t r 1 i n t e r r u p t 1 : s e r i a l i / o 3 r e c e i v e i n t e r r u p t a d c o n v e r t e r / s e r i a l i / o 3 t r a n s m i t i n t e r r u p t s o u r c e s e l e c t i o n b i t 0 : a - d c o n v e r t e r i n t e r r u p t 1 : s e r i a l i / o 3 t r a n s m i t i n t e r r u p t i n t e r r u p t s o u r c e s e l e c t i o n r e g i s t e r ( d o n o t w r i t e 1 t o t h e s e b i t s s i m u l t a n e o u s l y . ) ( i n t s e l : a d d r e s s 0 0 3 9 1 6 ) b 0 ( d o n o t w r i t e 1 t o t h e s e b i t s s i m u l t a n e o u s l y . ) b 7 b 0 b 7 b 0 b 7 b 0 b 7 b 0 b 7 b 0
34 3803/3804 group single-chip 8-bit cmos microcomputer mitsubishi microcomputers timers l 8-bit timers the 3803/3804 group has four 8-bit timers: timer 1, timer 2, timer x, and timer y. the timer 1 and timer 2 use one prescaler in common, and the timer x and timer y use each prescaler. those are 8-bit prescalers. each of the timers and prescalers has a timer latch or a prescaler latch. the division ratio of each timer or prescaler is given by 1/(n + 1), where n is the value in the corresponding timer or prescaler latch. all timers are down-counters. when the timer reaches 00 16 , an underflow occurs at the next count pulse and the contents of the corresponding timer latch are reloaded into the timer and the count is continued. when the timer underflows, the interrupt re- quest bit corresponding to that timer is set to 1. l timer divider each of the prescaler 12, the prescaler x and the prescaler y has a divider for the count source. the x in or x cin , which is switched by the cpu mode register (bits 7 and 6 at address 003b 16 ), can be used as the divider count source. each division ratio is con- trolled by the timer 12, x count source selection register and the timer y, z count source selection register. it can be selected among 1/2, 1/4, 1/8, 1/16, 1/32, 1/64, 1/128, 1/256, 1/512 and 1/ 1024 of f(x in ) or f(x cin ); and f(x cin ). timer 1 and timer 2 the timer 1 and timer 2 can select the count source of prescaler 12 by the timer 12 count source selection bits of timer 12, x count source selection register (bits 3 to 0 at address 000e 16 ) among 1/ 2, 1/4, 1/8, 1/16, 1/32, 1/64, 1/128, 1/256, 1/512 and 1/1024 of f(x in ) or f(x cin ). the timer 1 and timer 2 counts the output of prescaler 12 and pe- riodically set the interrupt request bit. timer x and timer y the timer x can select the count source of prescaler x by the timer x count source selection bits of timer 12, x count source se- lection register (bits 7 to 4 at address 000e 16 ). the timer y can select the count source of prescaler y by the timer y count source selection bits of timer y, z count source se- lection register (bits 3 to 0 at address 000f 16 ). the timer x and timer y can each select one of four operating modes by setting the timer xy mode register (address 0023 16 ). (1) timer mode l mode selection this mode can be selected by setting 00 to the timer x operating mode bits (bits 1 and 0) and the timer y operating mode bits (bits 5 and 4) of the timer xy mode register (address 0023 16 ). the signal dividing oscillation frequency to the division ratio set into the divider is counted. l count source selection in high- or middle-speed mode, 1/2, 1/4, 1/8, 1/16, 1/32, 1/64, 1/ 128, 1/256, 1/512 or 1/1024 of f(x in ); or f(x cin ) can be selected as the count source. in low-speed mode, 1/2, 1/4, 1/8, 1/16, 1/32, 1/64, 1/128, 1/256, 1/ 512 or 1/1024 of f(x cin ); or f(x cin ) can be selected as the count source. l interrupt when an underflow occurs, the timer x interrupt request bit (bit 4) or timer y interrupt request bit (bit 5) of the interrupt request regis- ter 1 (address 003c 16 ) is set to 1. l explanation of operation the timer count operation is started by setting 0 to the timer x count stop bit (bit 3) and the timer y count stop bit (bit 7) of the timer xy mode register (address 0023 16 ). when the timer reaches 00 16 , an underflow occurs at the next count pulse and the contents of timer latch are reloaded into the timer and the count is continued. when writing data to the timer during count operation, the data is written only into the latch. then the new latch value is reloaded into the timer at the next underflow. (2) pulse output mode l mode selection this mode can be selected by setting 01 to the timer x operating mode bits (bits 1 and 0) and the timer y operating mode bits (bits 5 and 4) of the timer xy mode register (address 0023 16 ). l count source selection in high- or middle-speed mode, 1/2, 1/4, 1/8, 1/16, 1/32, 1/64, 1/ 128, 1/256, 1/512 or 1/1024 of f(x in ); or f(x cin ) can be selected as the count source. in low-speed mode, 1/2, 1/4, 1/8, 1/16, 1/32, 1/64, 1/128, 1/256, 1/ 512 or 1/1024 of f(x cin ); or f(x cin ) can be selected as the count source. l interrupt the interrupt at an underflow is the same as the timer modes. l explanation of operation the operation is the same as the timer modes. moreover the pulse which is inverted each time the timer underflows is output from cntr 0 /cntr 1 pin. when the cntr 0 active edge switch bit (bit 2) and the cntr 1 active edge switch bit (bit 6) of the timer xy mode register (address 0023 16 ) is 0, the output starts with h level. when it is 1, the output starts with l level. n precautions set the double-function port of cntr 0 /cntr 1 pin and port p5 4 / p5 5 to output in this mode. [during timer operation stop] the output from cntr 0 /cntr 1 pin is initialized to the level de- pending on cntr 0 /cntr 1 active edge switch bit by writing to the timer. [during timer operation enabled] when the value of the cntr 0 /cntr 1 active edge switch bit is
35 3803/3804 group single-chip 8-bit cmos microcomputer mitsubishi microcomputers changed, the output level of cntr 0 /cntr 1 pin is inverted. (3) event counter mode l mode selection this mode can be selected by setting 10 to the timer x operating mode bits (bits 1 and 0) and the timer y operating mode bits (bits 5 and 4) of the timer xy mode register (address 0023 16 ). the valid edge for the count operation depends on the cntr 0 ac- tive edge switch bit (bit 2) or the cntr 1 active edge switch bit (bit 6) of the timer xy mode register (address 0023 16 ). when it is 0, the rising edge is valid. when it is 1, the falling edge is valid. l interrupt the interrupt at an underflow is the same as the timer modes. l explanation of operation the operation is the same as the timer modes. set the double-function port of cntr 0 /cntr 1 pin and port p5 4 / p5 5 to input in this mode. (4) pulse width measurement mode l mode selection this mode can be selected by setting 11 to the timer x operating mode bits (bits 1 and 0) and the timer y operating mode bits (bits 5 and 4) of the timer xy mode register (address 0023 16 ). l count source selection in high- or middle-speed mode, 1/2, 1/4, 1/8, 1/16, 1/32, 1/64, 1/ 128, 1/256, 1/512 or 1/1024 of f(x in ); or f(x cin ) can be selected as the count source. in low-speed mode, 1/2, 1/4, 1/8, 1/16, 1/32, 1/64, 1/128, 1/256, 1/ 512 or 1/1024 of f(x cin ); or f(x cin ) can be selected as the count source. l explanation of operation [during timer operation stop] select the count source. next, select the term of the pulse widths to be measured. when the cntr 0 active edge switch bit (bit 2) or the cntr 1 active edge switch bit (bit 6) of the timer xy mode reg- ister (address 0023 16 ) is 1, the timer counts during the term of one falling edge of cntr 0 /cntr 1 pin input until the next rising edge of input (l term). when it is 0, the timer counts during the term of one rising edge input until the next falling edge input (h term). [during timer operation enabled] the pulse width measurement starts by setting 0 to the timer x count stop bit (bit 3) or the timer y count stop bit (bit 7) of the timer xy mode register (address 0023 16 ), and the timer counts down from the value that was set to the timer before the start of mea- surement. when the valid edge of measurement completion is detected, the 1s complement of the timer value is written to the timer latch. when the valid edge of measurement start/completion is detected, ff 16 is set to the prescaler and the timer. furthermore when the timer underflows, the timer x/y interrupt re- quest occurs and ff 16 is set to the prescaler and the timer. the measured value is retained until the next measurement comple- tion. n precautions set the double-function port of cntr 0 /cntr 1 pin and port p5 4 / p5 5 to input in this mode. a read-out of timer value is impossible in this mode. the timer can be written to only during timer stop (no measurement of pulse widths). since the timer latch in this mode is specialized for the read-out of measured values, do not perform any write operation during mea- surement. n precautions regarding all modes the count operation can be stopped by setting 1 to the timer x count stop bit (bit 3) and the timer y count stop bit (bit 7) of the timer xy mode register (address 0023 16 ). the interrupt request bit is set to 1 each time the timer underflows. when switching the count source by the timer 12, x and y count source selection bits, the value of timer count is altered in incon- siderable amount owing to generating of thin pulses on the count input signals. therefore, select the timer count source before setting the value to the prescaler and the timer..
36 3803/3804 group single-chip 8-bit cmos microcomputer mitsubishi microcomputers fig. 27 block diagram of timer x, timer y, timer 1, and timer 2 q q ? ? p 5 4 / c n t r 0 q q p 5 5 / c n t r 1 ? 1 r r t t f ( x c i n ) f ( x c i n ) c l o c k f o r t i m e r 1 2 x i n x c i n ( 1 / 2 , 1 / 4 , 1 / 8 , 1 / 1 6 , 1 / 3 2 , 1 / 6 4 , 1 / 1 2 8 , 1 / 2 5 6 , 1 / 5 1 2 , 1 / 1 0 2 4 ) d i v i d e r c l o c k f o r t i m e r y c l o c k f o r t i m e r x c o u n t s o u r c e s e l e c t i o n b i t c n t r 0 a c t i v e e d g e s w i t c h b i t p o r t p 5 4 d i r e c t i o n r e g i s t e r p u l s e o u t p u t m o d e p o r t p 5 4 l a t c h c n t r 0 a c t i v e e d g e s w i t c h b i t t o g g l e f l i p - f l o p p u l s e w i d t h m e a s u r e m e n t m o d e t i m e r m o d e p u l s e o u t p u t m o d e t i m e r x c o u n t s t o p b i t p r e s c a l e r x ( 8 ) p r e s c a l e r x l a t c h ( 8 ) d a t a b u s t i m e r x l a t c h ( 8 ) t i m e r x ( 8 ) t o t i m e r x i n t e r r u p t r e q u e s t b i t t o c n t r 0 i n t e r r u p t r e q u e s t b i t t i m e r x l a t c h w r i t e p u l s e p u l s e o u t p u t m o d e c l o c k f o r t i m e r y c o u n t s o u r c e s e l e c t i o n b i t e v e n t c o u n t e r m o d e p u l s e w i d t h m e a s u r e m e n t m o d e t i m e r m o d e p u l s e o u t p u t m o d e t i m e r y c o u n t s t o p b i t e v e n t c o u n t e r m o d e ? 1 c n t r 1 a c t i v e e d g e s w i t c h b i t p r e s c a l e r y ( 8 ) p r e s c a l e r y l a t c h ( 8 ) d a t a b u s t i m e r y l a t c h ( 8 ) t i m e r y ( 8 ) t o t i m e r y i n t e r r u p t r e q u e s t b i t t o c n t r 1 i n t e r r u p t r e q u e s t b i t p o r t p 5 5 d i r e c t i o n r e g i s t e r p u l s e o u t p u t m o d e p o r t p 5 5 l a t c h ? ? c n t r 1 a c t i v e e d g e s w i t c h b i t t o g g l e f l i p - f l o p t i m e r y l a t c h w r i t e p u l s e p u l s e o u t p u t m o d e t i m e r 2 l a t c h ( 8 ) t i m e r 2 ( 8 ) t o t i m e r 2 i n t e r r u p t r e q u e s t b i t t o t i m e r 1 i n t e r r u p t r e q u e s t b i t c l o c k f o r t i m e r 1 2 p r e s c a l e r 1 2 ( 8 ) p r e s c a l e r 1 2 l a t c h ( 8 ) d a t a b u s t i m e r 1 l a t c h ( 8 ) t i m e r 1 ( 8 )
37 3803/3804 group single-chip 8-bit cmos microcomputer mitsubishi microcomputers fig. 28 structure of timer xy mode register t i m e r x y m o d e r e g i s t e r ( t m : a d d r e s s 0 0 2 3 1 6 ) t i m e r x o p e r a t i n g m o d e b i t s b 1b 0 00 : t i m e r m o d e 01 : p u l s e o u t p u t m o d e 10 : e v e n t c o u n t e r m o d e 11 : p u l s e w i d t h m e a s u r e m e n t m o d e c n t r 0 a c t i v e e d g e s w i t c h b i t 0 : i n t e r r u p t a t f a l l i n g e d g e c o u n t a t r i s i n g e d g e i n e v e n t c o u n t e r m o d e 1 : i n t e r r u p t a t r i s i n g e d g e c o u n t a t f a l l i n g e d g e i n e v e n t c o u n t e r m o d e t i m e r x c o u n t s t o p b i t 0 : c o u n t s t a r t 1 : c o u n t s t o p t i m e r y o p e r a t i n g m o d e b i t s b 5b 4 00 : t i m e r m o d e 01 : p u l s e o u t p u t m o d e 10 : e v e n t c o u n t e r m o d e 11 : p u l s e w i d t h m e a s u r e m e n t m o d e c n t r 1 a c t i v e e d g e s w i t c h b i t 0 : i n t e r r u p t a t f a l l i n g e d g e c o u n t a t r i s i n g e d g e i n e v e n t c o u n t e r m o d e 1 : i n t e r r u p t a t r i s i n g e d g e c o u n t a t f a l l i n g e d g e i n e v e n t c o u n t e r m o d e t i m e r y c o u n t s t o p b i t 0 : c o u n t s t a r t 1 : c o u n t s t o p b 7 b 0
38 3803/3804 group single-chip 8-bit cmos microcomputer mitsubishi microcomputers fig. 29 structure of timer 12, x and timer y, z count source selection registers t i m e r 1 2 , x c o u n t s o u r c e s e l e c t i o n r e g i s t e r ( t 1 2 x c s s : a d d r e s s 0 0 0 e 1 6 ) t i m e r 1 2 c o u n t s o u r c e s e l e c t i o n b i t s b 3 b 2 b 1 b 0 0000: f ( x i n ) / 2 o r f ( x c i n ) / 21 0 1 1 : 0001: f ( x i n ) / 4 o r f ( x c i n ) / 41 1 0 0 : 0010: f ( x i n ) / 8 o r f ( x c i n ) / 81 1 0 1 :n o t u s e d 0011: f ( x i n ) / 1 6 o r f ( x c i n ) / 1 61 1 1 0 : 0100: f ( x i n ) / 3 2 o r f ( x c i n ) / 3 21 1 1 1 : 0101: f ( x i n ) / 6 4 o r f ( x c i n ) / 6 4 0110: f ( x i n ) / 1 2 8 o r f ( x c i n ) / 1 2 8 0111: f ( x i n ) / 2 5 6 o r f ( x c i n ) / 2 5 6 1000: f ( x i n ) / 5 1 2 o r f ( x c i n ) / 5 1 2 1001: f ( x i n ) / 1 0 2 4 o r f ( x c i n ) / 1 0 2 4 1010: n o t u s e d b 7 b 0 t i m e r x c o u n t s o u r c e s e l e c t i o n b i t s b 7 b 6 b 5 b 4 0000: f ( x i n ) / 2 o r f ( x c i n ) / 21 0 1 1 : 0001: f ( x i n ) / 4 o r f ( x c i n ) / 41 1 0 0 : 0010: f ( x i n ) / 8 o r f ( x c i n ) / 81 1 0 1 :n o t u s e d 0011: f ( x i n ) / 1 6 o r f ( x c i n ) / 1 61 1 1 0 : 0100: f ( x i n ) / 3 2 o r f ( x c i n ) / 3 21 1 1 1 : 0101: f ( x i n ) / 6 4 o r f ( x c i n ) / 6 4 0110: f ( x i n ) / 1 2 8 o r f ( x c i n ) / 1 2 8 0111: f ( x i n ) / 2 5 6 o r f ( x c i n ) / 2 5 6 1000: f ( x i n ) / 5 1 2 o r f ( x c i n ) / 5 1 2 1001: f ( x i n ) / 1 0 2 4 o r f ( x c i n ) / 1 0 2 4 1010: f ( x c i n ) t i m e r y , z c o u n t s o u r c e s e l e c t i o n r e g i s t e r ( t y z c s s : a d d r e s s 0 0 0 f 1 6 ) t i m e r y c o u n t s o u r c e s e l e c t i o n b i t s b 3 b 2 b 1 b 0 0000: f ( x i n ) / 2 o r f ( x c i n ) / 21 0 1 1 : 0001: f ( x i n ) / 4 o r f ( x c i n ) / 41 1 0 0 : 0010: f ( x i n ) / 8 o r f ( x c i n ) / 81 1 0 1 :n o t u s e d 0011: f ( x i n ) / 1 6 o r f ( x c i n ) / 1 61 1 1 0 : 0100: f ( x i n ) / 3 2 o r f ( x c i n ) / 3 21 1 1 1 : 0101: f ( x i n ) / 6 4 o r f ( x c i n ) / 6 4 0110: f ( x i n ) / 1 2 8 o r f ( x c i n ) / 1 2 8 0111: f ( x i n ) / 2 5 6 o r f ( x c i n ) / 2 5 6 1000: f ( x i n ) / 5 1 2 o r f ( x c i n ) / 5 1 2 1001: f ( x i n ) / 1 0 2 4 o r f ( x c i n ) / 1 0 2 4 1010: f ( x c i n ) b 7 b 0 t i m e r z c o u n t s o u r c e s e l e c t i o n b i t s b 7 b 6 b 5 b 4 0000: f ( x i n ) / 2 o r f ( x c i n ) / 21 0 1 1 : 0001: f ( x i n ) / 4 o r f ( x c i n ) / 41 1 0 0 : 0010: f ( x i n ) / 8 o r f ( x c i n ) / 81 1 0 1 :n o t u s e d 0011: f ( x i n ) / 1 6 o r f ( x c i n ) / 1 61 1 1 0 : 0100: f ( x i n ) / 3 2 o r f ( x c i n ) / 3 21 1 1 1 : 0101: f ( x i n ) / 6 4 o r f ( x c i n ) / 6 4 0110: f ( x i n ) / 1 2 8 o r f ( x c i n ) / 1 2 8 0111: f ( x i n ) / 2 5 6 o r f ( x c i n ) / 2 5 6 1000: f ( x i n ) / 5 1 2 o r f ( x c i n ) / 5 1 2 1001: f ( x i n ) / 1 0 2 4 o r f ( x c i n ) / 1 0 2 4 1010: f ( x c i n )
39 3803/3804 group single-chip 8-bit cmos microcomputer mitsubishi microcomputers l 16-bit timers the timer z is a 16-bit timer. when the timer reaches 0000 16 , an underflow occurs at the next count pulse and the corresponding timer latch is reloaded into the timer and the count is continued. when the timer underflows, the interrupt request bit corresponding to the timer z is set to 1. read and write operation to a 16-bit timer must be performed for both high- and low-order bytes. when reading a 16-bit timer, read from the high-order byte first, followed by the low-order byte. when writing to a 16-bit timer, write to the low-order byte first, fol- lowed by the high-order byte. the 16-bit timer cannot perform the correct operation when reading during write operation, or when writing during read operation. the timer z can select the count source by the timer z count source selection bits of timer y, z count source selection register (bits 7 to 4 at address 000f 16 ). timer z can select one of six operating modes by setting the timer z mode register (address 002a 16 ). (1) timer mode l mode selection this mode can be selected by setting 000 to the timer z operat- ing mode bits (bits 2 to 0) of the timer z mode register (address 002a 16 ). l count source selection in high- or middle-speed mode, 1/2, 1/4, 1/8, 1/16, 1/32, 1/64, 1/ 128, 1/256, 1/512 or 1/1024 of f(x in ); or f(x cin ) can be selected as the count source. in low-speed mode, 1/2, 1/4, 1/8, 1/16, 1/32, 1/64, 1/128, 1/256, 1/ 512 or 1/1024 of f(x cin ); or f(x cin ) can be selected as the count source. l interrupt when an underflow occurs, the int 0 /timer z interrupt request bit (bit 0) of the interrupt request register 1 (address 003c 16 ) is set to 1. l explanation of operation after reset release, the timer z count stop bit (bit 6) of the timer z mode register (address 002a 16 ) is 1 and the timer stops. during timer stop, usually write data to a latch and a timer at the same time to set the timer value. the timer count operation is started by setting 0 to the timer z count stop bit (bit 6) of the timer z mode register (address 002a 16 ). when the timer reaches 0000 16 , an underflow occurs at the next count pulse and the contents of timer latch are reloaded into the timer and the count is continued. when writing data to the timer during operation, the data is written only into the latch. then the new latch value is reloaded into the timer at the next underflow. (2) event counter mode l mode selection this mode can be selected by setting 000 to the timer z operat- ing mode bits (bits 2 to 0) and the timer/event counter mode switch bit (bit 7) of the timer z mode register (address 002a 16 ). the valid edge for the count operation depends on the cntr 2 ac- tive edge switch bit (bit 5) of the timer z mode register (address 002a 16 ). when it is 0, the rising edge is valid. when it is 1, the falling edge is valid. l interrupt the interrupt at an underflow is the same as the timer modes. l explanation of operation the operation is the same as the timer modes. set the double-function port of cntr 2 pin and port p4 7 to input in this mode. figure 32 shows the timing chart of the timer/event counter mode. (3) pulse output mode l mode selection this mode can be selected by setting 001 to the timer z operat- ing mode bits (bits 2 to 0) of the timer z mode register (address 002a 16 ). l count source selection in high- or middle-speed mode, 1/2, 1/4, 1/8, 1/16, 1/32, 1/64, 1/ 128, 1/256, 1/512 or 1/1024 of f(x in ); or f(x cin ) can be selected as the count source. in low-speed mode, 1/2, 1/4, 1/8, 1/16, 1/32, 1/64, 1/128, 1/256, 1/ 512 or 1/1024 of f(x cin ); or f(x cin ) can be selected as the count source. l interrupt the interrupt at an underflow is the same as the timer modes. l explanation of operation the operation is the same as the timer modes. moreover the pulse which is inverted each time the timer underflows is output from cntr 2 pin. when the cntr 2 active edge switch bit (bit 5) of the timer z mode register (address 002a 16 ) is 0, the output starts with h level. when it is 1, the output starts with l level. n precautions set the double-function port of cntr 2 pin and port p4 7 to output in this mode. [during timer operation stop] the output from cntr 2 pin is initialized to the level depending on cntr 2 active edge switch bit by writing to the timer. [during timer operation enabled] when the value of the cntr 2 active edge switch bit is changed, the output level of cntr 2 pin is inverted. figure 33 shows the timing chart of the pulse output mode.
40 3803/3804 group single-chip 8-bit cmos microcomputer mitsubishi microcomputers (4) pulse period measurement mode l mode selection this mode can be selected by setting 010 to the timer z operat- ing mode bits (bits 2 to 0) of the timer z mode register (address 002a 16 ). l count source selection in high- or middle-speed mode, 1/2, 1/4, 1/8, 1/16, 1/32, 1/64, 1/128, 1/256, 1/512 or 1/1024 of f(x in ); or f(x cin ) can be selected as the count source. in low-speed mode, 1/2, 1/4, 1/8, 1/16, 1/32, 1/64, 1/128, 1/256, 1/512 or 1/1024 of f(x cin ); or f(x cin ) can be selected as the count source. l interrupt the interrupt at an underflow is the same as the timer modes. when the pulse period measurement is completed, the int 4 / cntr 2 interrupt request bit (bit 5) of the interrupt request register 2 (address 003d 16 ) is set to 1. l explanation of operation [during timer operation stop] select the count source. next, select the term of the pulse period to be measured. when the cntr 2 active edge switch bit (bit 5) of the timer z mode register (address 002a 16 ) is 0, the timer counts during the term of one falling edge of cntr 2 pin input until the next falling edge of input. when it is 1, the timer counts during the term of one rising edge input until the next rising edge input. [during timer operation enabled] the pulse period measurement starts by setting 0 to the timer z count stop bit (bit 6) of the timer z mode register (address 002a 16 ), and the timer counts down from the value that was set to the timer before the start of measurement. when the valid edge of measurement completion/start is detected, the 1s complement of the timer value is written to the timer latch and ffff 16 is set to the timer. furthermore when the timer underflows, the timer z interrupt re- quest occurs and ffff 16 is set to the timer. the measured value is retained until the next measurement completion. n precautions set the double-function port of cntr 2 pin and port p4 7 to input in this mode. a read-out of timer value is impossible in this mode. the timer can be written to only during timer stop (no measurement of pulse pe- riod). since the timer latch in this mode is specialized for the read-out of measured values, do not perform any write operation during mea- surement. ffff 16 is set to the timer when the timer underflows or when the valid edge of measurement start/completion is detected. conse- quently, the timer value at start of pulse period measurement depends on the timer value just before measurement start. figure 34 shows the timing chart of the pulse period measurement mode. (5) pulse width measurement mode l mode selection this mode can be selected by setting 011 to the timer z operat- ing mode bits (bits 2 to 0) of the timer z mode register (address 002a 16 ). l count source selection in high- or middle-speed mode, 1/2, 1/4, 1/8, 1/16, 1/32, 1/64, 1/128, 1/256, 1/512 or 1/1024 of f(x in ); or f(x cin ) can be selected as the count source. in low-speed mode, 1/2, 1/4, 1/8, 1/16, 1/32, 1/64, 1/128, 1/256, 1/512 or 1/1024 of f(x cin ); or f(x cin ) can be selected as the count source. l interrupt the interrupt at an underflow is the same as the timer modes. when the pulse widths measurement is completed, the int 4 / cntr 2 interrupt request bit (bit 5) of the interrupt request register 2 (address 003d 16 ) is set to 1. l explanation of operation [during timer operation stop] select the count source. next, select the term of the pulse width to be measured. when the cntr 2 active edge switch bit (bit 5) of the timer z mode register (address 002a 16 ) is 1, the timer counts during the term of one falling edge of cntr 2 pin input until the next rising edge of input (l term). when it is 0, the timer counts during the term of one rising edge input until the next falling edge input (h term). [during timer operation enabled] the pulse width measurement starts by setting 0 to the timer z count stop bit (bit 6) of the timer z mode register (address 002a 16 ), and the timer counts down from the value that was set to the timer before the start of measurement. when the valid edge of measurement completion is detected, the 1s complement of the timer value is written to the timer latch. when the valid edge of measurement start/completion is detected, ffff 16 is set to the timer. furthermore when the timer underflows, the timer z interrupt re- quest occurs and ffff 16 is set to the timer. the measured value is retained until the next measurement completion. n precautions set the double-function port of cntr 2 pin and port p4 7 to input in this mode. a read-out of timer value is impossible in this mode. the timer can be written to only during timer stop (no measurement of pulse widths). since the timer latch in this mode is specialized for the read-out of measured values, do not perform any write operation during mea- surement. ffff 16 is set to the timer when the timer underflows or when the valid edge of measurement start/completion is detected. conse- quently, the timer value at start of pulse width measurement depends on the timer value just before measurement start. figure 35 shows the timing chart of the pulse width measurement mode.
41 3803/3804 group single-chip 8-bit cmos microcomputer mitsubishi microcomputers (6) programmable waveform generating mode l mode selection this mode can be selected by setting 100 to the timer z operat- ing mode bits (bits 2 to 0) of the timer z mode register (address 002a 16 ). l count source selection in high- or middle-speed mode, 1/2, 1/4, 1/8, 1/16, 1/32, 1/64, 1/128, 1/256, 1/512 or 1/1024 of f(x in ); or f(x cin ) can be selected as the count source. in low-speed mode, 1/2, 1/4, 1/8, 1/16, 1/32, 1/64, 1/128, 1/256, 1/ 512 or 1/1024 of f(x cin ); or f(x cin ) can be selected as the count source. l interrupt the interrupt at an underflow is the same as the timer modes. l explanation of operation the operation is the same as the timer modes. moreover the timer outputs the data set in the output level latch (bit 4) of the timer z mode register (address 002a 16 ) from the cntr 2 pin each time the timer underflows. changing the value of the output level latch and the timer latch af- ter an underflow makes it possible to output an optional waveform from the cntr 2 pin. n precautions set the double-function port of cntr 2 pin and port p4 7 to output in this mode. figure 36 shows the timing chart of the programmable waveform generating mode. (7) programmable one-shot generating mode l mode selection this mode can be selected by setting 101 to the timer z operat- ing mode bits (bits 2 to 0) of the timer z mode register (address 002a 16 ). l count source selection in high- or middle-speed mode, 1/2, 1/4, 1/8, 1/16, 1/32, 1/64, 1/ 128, 1/256, 1/512 or 1/1024 of f(x in ); or f(x cin ) can be selected as the count source. l interrupt the interrupt at an underflow is the same as the timer modes. the trigger to generate one-shot pulse can be selected by the int 1 active edge selection bit (bit 1) of the interrupt edge selection register (address 003a 16 ). when it is 0, the falling edge active is selected; when it is 1, the rising edge active is selected. when the valid edge of the int 1 pin is detected, the int 1 interrupt request bit (bit 1) of the interrupt request register 1 (address 003c 16 ) is set to 1. l explanation of operation ?h one-shot pulse; bit 5 of timer z mode register = 0 [during timer operation stop] the output level of cntr 2 pin is initialized to l at mode selec- tion. set the one-shot pulse width to the registers of timer z low-order and high-order. trigger generating during timer stop (input signal to int 1 pin) is in- valid. [during timer operation enabled] when trigger generating is detected, h is output from the cntr 2 pin. when an underflow occurs, l is output. ?l one-shot pulse; bit 5 of timer z mode register = 1 [during timer operation stop] the output level of cntr 2 pin is initialized to h at mode selec- tion. set the one-shot pulse width to the registers of timer z low-order and high-order. trigger generating during timer stop (input signal to int 1 pin) is in- valid. [during timer operation enabled] when trigger generating is detected, l is output from the cntr 2 pin. when an underflow occurs, h is output. n precautions set the double-function port of cntr 2 pin and port p4 7 to output, and of int 1 pin and port p4 2 to input in this mode. this mode cannot be used in low-speed mode. if the value of the cntr 2 active edge switch bit is changed during one-shot generating enabled or generating one-shot pulse, then the output level from cntr 2 pin changes. figure 37 shows the timing chart of the programmable one-shot generating mode. n notes regarding all modes l timer z write control which write control can be selected by the timer z write control bit (bit 3) of the timer z mode register (address 002a 16 ), writing data to both the latch and the timer at the same time or writing data only to the latch. when the operation writing data only to the latch is selected, the value is set to the timer latch by writing data to the address of timer z and the timer is updated at next underflow. after reset re- lease, the operation writing data to both the latch and the timer at the same time is selected, and the value is set to both the latch and the timer at the same time by writing data to the address of timer z. in the case of writing data only to the latch, if writing data to the latch and an underflow are performed almost at the same time, the timer value may become undefined. l timer z read control a read-out of timer value is impossible in pulse period measure- ment mode and pulse width measurement mode. in the other modes, a read-out of timer value is possible regardless of count operating or stopped. however, a read-out of timer latch value is impossible. l switch of interrupt active edge of cntr 2 and int 1 each interrupt active edge depends on setting of the cntr 2 ac- tive edge switch bit and the int 1 active edge selection bit. l switch of count source when switching the count source by the timer z count source se- lection bits, the value of timer count is altered in inconsiderable amount owing to generating of thin pulses on the count input sig- nals. therefore, select the timer count source before setting the value to the prescaler and the timer.
42 3803/3804 group single-chip 8-bit cmos microcomputer mitsubishi microcomputers fig. 30 block diagram of timer z ? ? p 4 2 / i n t 1 p 4 7 / c n t r 2 ? 1 0 0 1 1 0 0 1 0 1 @ @ f ( x c i n ) x i n x c i n o u t p u t l e v e l l a t c h p r o g r a m m a b l e o n e - s h o t g e n e r a t i n g m o d e p r o g r a m m a b l e o n e - s h o t g e n e r a t i n g c i r c u i t c n t r 2 a c t i v e e d g e s w i t c h b i t p r o g r a m m a b l e o n e - s h o t g e n e r a t i n g m o d e d a t a b u s t o t i m e r z i n t e r r u p t r e q u e s t b i t t o c n t r 2 i n t e r r u p t r e q u e s t b i t t o i n t 1 i n t e r r u p t r e q u e s t b i t p r o g r a m m a b l e w a v e f o r m g e n e r a t i n g m o d e p u l s e o u t p u t m o d e c n t r 2 a c t i v e e d g e s w i t c h b i t p u l s e o u t p u t m o d e t i m e r z l o w - o r d e r l a t c h t i m e r z l o w - o r d e r t i m e r z h i g h - o r d e r l a t c h t i m e r z h i g h - o r d e r t i m e r z o p e r a t i n g m o d e b i t s p o r t p 4 7 d i r e c t i o n r e g i s t e r p o r t p 4 7 l a t c h p u l s e p e r i o d m e a s u r e m e n t m o d e p u l s e w i d t h m e a s u r e m e n t m o d e e d g e d e t e c t i o n c i r c u i t t i m e r z c o u n t s t o p b i t c o u n t s o u r c e s e l e c t i o n b i t ( 1 / 2 , 1 / 4 , 1 / 8 , 1 / 1 6 , 1 / 3 2 , 1 / 6 4 , 1 / 1 2 8 , 1 / 2 5 6 , 1 / 5 1 2 , 1 / 1 0 2 4 ) d i v i d e r c l o c k f o r t i m e r z c n t r 2 a c t i v e e d g e s w i t c h b i t d q t tq q s ? ?
43 3803/3804 group single-chip 8-bit cmos microcomputer mitsubishi microcomputers fig. 31 structure of timer z mode register t i m e r z m o d e r e g i s t e r ( t z m : a d d r e s s 0 0 2 a 1 6 ) t i m e r z o p e r a t i n g m o d e b i t s b 2 b 1 b 0 000: t i m e r / e v e n t c o u n t e r m o d e 001: p u l s e o u t p u t m o d e 010: p u l s e p e r i o d m e a s u r e m e n t m o d e 011: p u l s e w i d t h m e a s u r e m e n t m o d e 100: p r o g r a m m a b l e w a v e f o r m g e n e r a t i n g m o d e 101: p r o g r a m m a b l e o n e - s h o t g e n e r a t i n g m o d e 110: n o t a v a i l a b l e 111: n o t a v a i l a b l e t i m e r z w r i t e c o n t r o l b i t 0 : w r i t i n g d a t a t o b o t h l a t c h a n d t i m e r s i m u l t a n e o u s l y 1 : w r i t i n g d a t a o n l y t o l a t c h o u t p u t l e v e l l a t c h 0 : l o u t p u t 1 : h o u t p u t c n t r 2 a c t i v e e d g e s w i t c h b i t 0 : e v e n t c o u n t e r m o d e : c o u n t a t r i s i n g e d g e p u l s e o u t p u t m o d e : s t a r t o u t p u t t i n g h p u l s e p e r i o d m e a s u r e m e n t m o d e : m e a s u r e m e n t b e t w e e n t w o f a l l i n g e d g e s p u l s e w i d t h m e a s u r e m e n t m o d e : m e a s u r e m e n t o f h t e r m p r o g r a m m a b l e o n e - s h o t g e n e r a t i n g m o d e : a f t e r s t a r t o u t p u t t i n g l , h o n e - s h o t p u l s e g e n e r a t e d i n t e r r u p t a t f a l l i n g e d g e 1 : e v e n t c o u n t e r m o d e : c o u n t a t f a l l i n g e d g e p u l s e o u t p u t m o d e : s t a r t o u t p u t t i n g l p u l s e p e r i o d m e a s u r e m e n t m o d e : m e a s u r e m e n t b e t w e e n t w o r i s i n g e d g e s p u l s e w i d t h m e a s u r e m e n t m o d e : m e a s u r e m e n t o f l t e r m p r o g r a m m a b l e o n e - s h o t g e n e r a t i n g m o d e : a f t e r s t a r t o u t p u t t i n g h , l o n e - s h o t p u l s e g e n e r a t e d i n t e r r u p t a t r i s i n g e d g e t i m e r z c o u n t s t o p b i t 0 : c o u n t s t a r t 1 : c o u n t s t o p t i m e r / e v e n t c o u n t e r m o d e s w i t c h b i t 0 : t i m e r m o d e 1 : e v e n t c o u n t e r m o d e b 7 b 0
44 3803/3804 group single-chip 8-bit cmos microcomputer mitsubishi microcomputers fig. 32 timing chart of timer/event counter mode f f f f 1 6 0 0 0 0 1 6 t l t r t r t r t l : v a l u e s e t t o t i m e r l a t c h t r : t i m e r i n t e r r u p t r e q u e s t f f f f 1 6 0 0 0 0 1 6 t l t l : v a l u e s e t t o t i m e r l a t c h t r : t i m e r i n t e r r u p t r e q u e s t c n t r 2 : c n t r 2 i n t e r r u p t r e q u e s t ( c n t r 2 a c t i v e e d g e s w i t c h b i t = 0 ; f a l l i n g e d g e a c t i v e ) t r t rt rt r w a v e f o r n o u t p u t f r o m c n t r 2 p i n c n t r 2 c n t r 2 fig. 33 timing chart of pulse output mode
45 3803/3804 group single-chip 8-bit cmos microcomputer mitsubishi microcomputers fig. 34 timing chart of pulse period measurement mode (measuring term between two rising edges) f f f f 1 6 0 0 0 0 1 6 t 3 t rt r t 2 t 1 c n t r 2 c n t r 2 c n t r 2 c n t r 2 f f f f 1 6 + t 1 t 2 t 3 f f f f 1 6 s i g n a l in p u t f r o m c n t r 2 p i n c n t r 2 o f r i s i n g e d g e a c t i v e t r : t i m e r i n t e r r u p t r e q u e s t c n t r 2 : c n t r 2 i n t e r r u p t r e q u e s t f f f f 1 6 0 0 0 0 1 6 t 3 t r t 2 t 1 c n t r 2 c n t r 2 c n t r 2 f f f f 1 6 + t 2 t 1 t 3 c n t r 2 i n t e r r u p t o f r i s i n g e d g e a c t i v e ; m e a s u r e m e n t o f l w i d t h t r : t i m e r i n t e r r u p t r e q u e s t c n t r 2 : c n t r 2 i n t e r r u p t r e q u e s t s i g n a l i n p u t f r o m c n t r 2 p i n fig. 35 timing chart of pulse width measurement mode (measuring l term)
46 3803/3804 group single-chip 8-bit cmos microcomputer mitsubishi microcomputers fig. 36 timing chart of programmable waveform generating mode f f f f 1 6 0 0 0 0 1 6 t 3 t 2 t 1 t 2 t 3 l l t 1 t rt rt rt r c n t r 2 c n t r 2 s i g n a l o u t p u t f r o m c n t r 2 p i n l : t i m e r i n i t i a l v a l u e t r : t i m e r i n t e r r u p t r e q u e s t c n t r 2 : c n t r 2 i n t e r r u p t r e q u e s t ( c n t r 2 a c t i v e e d g e s w i t c h b i t = 0 ; f a l l i n g e d g e a c t i v e ) fig. 37 timing chart of programmable one-shot generating mode (h one-shot pulse generating) f f f f 1 6 l l t rt rt r ll c n t r 2 c n t r 2 s i g n a l o u t p u t f r o m c n t r 2 p i n l : o n e - s h o t p u l s e w i d t h t r : t i m e r i n t e r r u p t r e q u e s t c n t r 2 : c n t r 2 i n t e r r u p t r e q u e s t ( c n t r 2 a c t i v e e d g e s w i t c h b i t = 0 ; f a l l i n g e d g e a c t i v e ) s i g n a l i n p u t f r o m i n t 1 p i n
47 3803/3804 group single-chip 8-bit cmos microcomputer mitsubishi microcomputers serial i/o serial i/o1 serial i/o1 can be used as either clock synchronous or asynchro- nous (uart) serial i/o. a dedicated timer is also provided for baud rate generation. (1) clock synchronous serial i/o mode clock synchronous serial i/o1 mode can be selected by setting the serial i/o1 mode selection bit of the serial i/o1 control register (bit 6 of address 001a 16 ) to 1. for clock synchronous serial i/o, the transmitter and the receiver must use the same clock. if an internal clock is used, transfer is started by a write signal to the transmit/receive buffer register. fig. 38 block diagram of clock synchronous serial i/o1 fig. 39 operation of clock synchronous serial i/o1 1 / 4 1 / 4 f / f p 4 6 / s c l k 1 s e r i a l i / o 1 s t a t u s r e g i s t e r s e r i a l i / o 1 c o n t r o l r e g i s t e r p 4 7 / s r d y 1 p 4 4 / r x d 1 p 4 5 / t x d 1 r e c e i v e b u f f e r r e g i s t e r 1 a d d r e s s 0 0 1 8 1 6 r e c e i v e s h i f t r e g i s t e r 1 r e c e i v e b u f f e r f u l l f l a g ( r b f ) r e c e i v e i n t e r r u p t r e q u e s t ( r i ) c l o c k c o n t r o l c i r c u i t s h i f t c l o c k s e r i a l i / o 1 s y n c h r o n o u s c l o c k s e l e c t i o n b i t f r e q u e n c y d i v i s i o n r a t i o 1 / ( n + 1 ) b a u d r a t e g e n e r a t o r 1 a d d r e s s 0 0 1 c 1 6 b r g c o u n t s o u r c e s e l e c t i o n b i t c l o c k c o n t r o l c i r c u i t f a l l i n g - e d g e d e t e c t o r t r a n s m i t b u f f e r r e g i s t e r 1 d a t a b u s a d d r e s s 0 0 1 8 1 6 s h i f t c l o c k t r a n s m i t s h i f t c o m p l e t i o n f l a g ( t s c ) t r a n s m i t b u f f e r e m p t y f l a g ( t b e ) t r a n s m i t i n t e r r u p t r e q u e s t ( t i ) t r a n s m i t i n t e r r u p t s o u r c e s e l e c t i o n b i t a d d r e s s 0 0 1 9 1 6 d a t a b u s a d d r e s s 0 0 1 a 1 6 t r a n s m i t s h i f t r e g i s t e r 1 f ( x i n ) ( f ( x c i n ) i n l o w - s p e e d m o d e ) d 7 d 7 d 0 d 1 d 2 d 3 d 4 d 5 d 6 d 0 d 1 d 2 d 3 d 4 d 5 d 6 r b f = 1 t s c = 1 t b e = 0 t b e = 1 t s c = 0 t r a n s f e r s h i f t c l o c k ( 1 / 2 t o 1 / 2 0 4 8 o f t h e i n t e r n a l c l o c k , o r a n e x t e r n a l c l o c k ) s e r i a l o u t p u t t x d 1 s e r i a l i n p u t r x d 1 w r i t e p u l s e t o r e c e i v e / t r a n s m i t b u f f e r r e g i s t e r ( a d d r e s s 0 0 1 8 1 6 ) o v e r r u n e r r o r ( o e ) d e t e c t i o n n o t e s 1 : a s t h e t r a n s m i t i n t e r r u p t ( t i ) , w h i c h c a n b e s e l e c t e d , e i t h e r w h e n t h e t r a n s m i t b u f f e r h a s e m p t i e d ( t b e = 1 ) o r a f t e r t h e t r a n s m i t s h i f t o p e r a t i o n h a s e n d e d ( t s c = 1 ) , b y s e t t i n g t h e t r a n s m i t i n t e r r u p t s o u r c e s e l e c t i o n b i t ( t i c ) o f t h e s e r i a l i / o 1 c o n t r o l r e g i s t e r . 2 : i f d a t a i s w r i t t e n t o t h e t r a n s m i t b u f f e r r e g i s t e r w h e n t s c = 0 , t h e t r a n s m i t c l o c k i s g e n e r a t e d c o n t i n u o u s l y a n d s e r i a l d a t a i s o u t p u t c o n t i n u o u s l y f r o m t h e t x d p i n . 3 : t h e r e c e i v e i n t e r r u p t ( r i ) i s s e t w h e n t h e r e c e i v e b u f f e r f u l l f l a g ( r b f ) b e c o m e s 1 . r e c e i v e e n a b l e s i g n a l s r d y 1
48 3803/3804 group single-chip 8-bit cmos microcomputer mitsubishi microcomputers (2) asynchronous serial i/o (uart) mode clock asynchronous serial i/o mode (uart) can be selected by clearing the serial i/o1 mode selection bit of the serial i/o1 control register to 0. eight serial data transfer formats can be selected, and the transfer formats used by a transmitter and receiver must be identical. the transmit and receive shift registers each have a buffer, but the two buffers have the same address in a memory. since the shift register cannot be written to or read from directly, transmit data is written to the transmit buffer register, and receive data is read from the receive buffer register. the transmit buffer register can also hold the next data to be transmitted, and the receive buffer register can hold a character while the next character is being received. fig. 40 block diagram of uart serial i/o1 f ( x i n ) 1 / 4 o e p ef e 1 / 1 6 1 / 1 6 d a t a b u s r e c e i v e b u f f e r r e g i s t e r 1 a d d r e s s 0 0 1 8 1 6 r e c e i v e s h i f t r e g i s t e r 1 r e c e i v e b u f f e r f u l l f l a g ( r b f ) r e c e i v e i n t e r r u p t r e q u e s t ( r i ) b a u d r a t e g e n e r a t o r f r e q u e n c y d i v i s i o n r a t i o 1 / ( n + 1 ) a d d r e s s 0 0 1 c 1 6 s t / s p / p a g e n e r a t o r t r a n s m i t b u f f e r r e g i s t e r 1 d a t a b u s t r a n s m i t s h i f t r e g i s t e r 1 a d d r e s s 0 0 1 8 1 6 t r a n s m i t s h i f t c o m p l e t i o n f l a g ( t s c ) t r a n s m i t b u f f e r e m p t y f l a g ( t b e ) t r a n s m i t i n t e r r u p t r e q u e s t ( t i ) a d d r e s s 0 0 1 9 1 6 s t d e t e c t o r s p d e t e c t o r u a r t c o n t r o l r e g i s t e r a d d r e s s 0 0 1 b 1 6 c h a r a c t e r l e n g t h s e l e c t i o n b i t a d d r e s s 0 0 1 a 1 6 b r g c o u n t s o u r c e s e l e c t i o n b i t t r a n s m i t i n t e r r u p t s o u r c e s e l e c t i o n b i t s e r i a l i / o 1 s y n c h r o n o u s c l o c k s e l e c t i o n b i t c l o c k c o n t r o l c i r c u i t c h a r a c t e r l e n g t h s e l e c t i o n b i t 7 b i t s 8 b i t s s e r i a l i / o 1 c o n t r o l r e g i s t e r p 4 6 / s c l k 1 s e r i a l i / o 1 s t a t u s r e g i s t e r p 4 4 / r x d 1 p 4 5 / t x d 1 ( f ( x c i n ) i n l o w - s p e e d m o d e ) fig. 41 operation of uart serial i/o1 t s c = 0 t b e = 1 r b f = 0 t b e = 0t b e = 0 r b f = 1 r b f = 1 s t d 0 d 1 s p d 0 d 1 s t s p t b e = 1 t s c = 1 s t d 0 d 1 s p d 0 d 1 s t s p transmit or receive cloc k transmit buffer write signal g e n e r a t e d a t 2 n d b i t i n 2 - s t o p - b i t m o d e 1 s t a r t b i t 7 o r 8 d a t a b i t 1 o r 0 p a r i t y b i t 1 o r 2 s t o p b i t ( s ) 1 : e r r o r f l a g d e t e c t i o n o c c u r s a t t h e s a m e t i m e t h a t t h e r b f f l a g b e c o m e s 1 ( a t 1 s t s t o p b i t , d u r i n g r e c e p t i o n ) . 2 : a s t h e t r a n s m i t i n t e r r u p t ( t i ) , w h e n e i t h e r t h e t b e o r t s c f l a g b e c o m e s 1 , c a n b e s e l e c t e d t o o c c u r d e p e n d i n g o n t h e s e t t i n g o f t h e t r a n s m i t i n t e r r u p t s o u r c e s e l e c t i o n b i t ( t i c ) o f t h e s e r i a l i / o 1 c o n t r o l r e g i s t e r . 3 : t h e r e c e i v e i n t e r r u p t ( r i ) i s s e t w h e n t h e r b f f l a g b e c o m e s 1 . 4 : a f t e r d a t a i s w r i t t e n t o t h e t r a n s m i t b u f f e r w h e n t s c = 1 , 0 . 5 t o 1 . 5 c y c l e s o f t h e d a t a s h i f t c y c l e a r e n e c e s s a r y u n t i l c h a n g i n g t o t s c = 0 . n o t e s ] ] serial output t x d 1 serial input r x d 1 receive buffer read signal
49 3803/3804 group single-chip 8-bit cmos microcomputer mitsubishi microcomputers [serial i/o1 control register (sio1con)] 001a 16 the serial i/o1 control register consists of eight control bits for the serial i/o function. [uart1 control register (uart1con)] 001b 16 the uart control register consists of four control bits (bits 0 to 3) which are valid when asynchronous serial i/o is selected and set the data format of an data transfer, and one bit (bit 4) which is al- ways valid and sets the output structure of the p4 5 /t x d 1 pin. [serial i/o1 status register (sio1sts)] 0019 16 the read-only serial i/o1 status register consists of seven flags (bits 0 to 6) which indicate the operating status of the serial i/o1 function and various errors. three of the flags (bits 4 to 6) are valid only in uart mode. the receive buffer full flag (bit 1) is cleared to 0 when the receive buffer register is read. if there is an error, it is detected at the same time that data is transferred from the receive shift register to the receive buffer reg- ister, and the receive buffer full flag is set. a write to the serial i/o1 status register clears all the error flags oe, pe, fe, and se (bit 3 to bit 6, respectively). writing 0 to the serial i/o1 enable bit sioe (bit 7 of the serial i/o1 control register) also clears all the status flags, including the error flags. bits 0 to 6 of the serial i/o1 status register are initialized to 0 at reset, but if the transmit enable bit (bit 4) of the serial i/o1 control register has been set to 1, the transmit shift completion flag (bit 2) and the transmit buffer empty flag (bit 0) become 1. [transmit buffer register 1/receive buffer register 1 (tb1/rb1)] 0018 16 the transmit buffer register 1 and the receive buffer register 1 are located at the same address. the transmit buffer is write-only and the receive buffer is read-only. if a character bit length is 7 bits, the msb of data stored in the receive buffer is 0. [baud rate generator 1 (brg1)] 001c 16 the baud rate generator determines the baud rate for serial trans- fer. the baud rate generator divides the frequency of the count source by 1/(n + 1), where n is the value written to the baud rate genera- tor.
50 3803/3804 group single-chip 8-bit cmos microcomputer mitsubishi microcomputers fig. 42 structure of serial i/o1 control registers b 7 b 7 t r a n s m i t b u f f e r e m p t y f l a g ( t b e ) 0 : b u f f e r f u l l 1 : b u f f e r e m p t y r e c e i v e b u f f e r f u l l f l a g ( r b f ) 0 : b u f f e r e m p t y 1 : b u f f e r f u l l t r a n s m i t s h i f t c o m p l e t i o n f l a g ( t s c ) 0 : t r a n s m i t s h i f t i n p r o g r e s s 1 : t r a n s m i t s h i f t c o m p l e t e d o v e r r u n e r r o r f l a g ( o e ) 0 : n o e r r o r 1 : o v e r r u n e r r o r p a r i t y e r r o r f l a g ( p e ) 0 : n o e r r o r 1 : p a r i t y e r r o r f r a m i n g e r r o r f l a g ( f e ) 0 : n o e r r o r 1 : f r a m i n g e r r o r s u m m i n g e r r o r f l a g ( s e ) 0 : ( o e ) u ( p e ) u ( f e ) = 0 1 : ( o e ) u ( p e ) u ( f e ) = 1 n o t u s e d ( r e t u r n s 1 w h e n r e a d ) s e r i a l i / o 1 s t a t u s r e g i s t e r s e r i a l i / o 1 c o n t r o l r e g i s t e r b 0 b 0 b r g c o u n t s o u r c e s e l e c t i o n b i t ( c s s ) 0 : f ( x i n ) ( f ( x c i n ) i n l o w - s p e e d m o d e ) 1 : f ( x i n ) / 4 ( f ( x c i n ) / 4 i n l o w - s p e e d m o d e ) s e r i a l i / o 1 s y n c h r o n o u s c l o c k s e l e c t i o n b i t ( s c s ) 0 : b r g o u t p u t d i v i d e d b y 4 w h e n c l o c k s y n c h r o n o u s s e r i a l i / o i s s e l e c t e d , b r g o u t p u t d i v i d e d b y 1 6 w h e n u a r t i s s e l e c t e d . 1 : e x t e r n a l c l o c k i n p u t w h e n c l o c k s y n c h r o n o u s s e r i a l i / o i s s e l e c t e d , e x t e r n a l c l o c k i n p u t d i v i d e d b y 1 6 w h e n u a r t i s s e l e c t e d . s r d y 1 o u t p u t e n a b l e b i t ( s r d y ) 0 : p 4 7 p i n o p e r a t e s a s n o r m a l i / o p i n 1 : p 4 7 p i n o p e r a t e s a s s r d y 1 o u t p u t p i n t r a n s m i t i n t e r r u p t s o u r c e s e l e c t i o n b i t ( t i c ) 0 : i n t e r r u p t w h e n t r a n s m i t b u f f e r h a s e m p t i e d 1 : i n t e r r u p t w h e n t r a n s m i t s h i f t o p e r a t i o n i s c o m p l e t e d t r a n s m i t e n a b l e b i t ( t e ) 0 : t r a n s m i t d i s a b l e d 1 : t r a n s m i t e n a b l e d r e c e i v e e n a b l e b i t ( r e ) 0 : r e c e i v e d i s a b l e d 1 : r e c e i v e e n a b l e d s e r i a l i / o 1 m o d e s e l e c t i o n b i t ( s i o m ) 0 : c l o c k a s y n c h r o n o u s ( u a r t ) s e r i a l i / o 1 : c l o c k s y n c h r o n o u s s e r i a l i / o s e r i a l i / o 1 e n a b l e b i t ( s i o e ) 0 : s e r i a l i / o d i s a b l e d ( p i n s p 4 4 t o p 4 7 o p e r a t e a s n o r m a l i / o p i n s ) 1 : s e r i a l i / o e n a b l e d ( p i n s p 4 4 t o p 4 7 o p e r a t e a s s e r i a l i / o p i n s ) b 7 u a r t 1 c o n t r o l r e g i s t e r c h a r a c t e r l e n g t h s e l e c t i o n b i t ( c h a s ) 0 : 8 b i t s 1 : 7 b i t s p a r i t y e n a b l e b i t ( p a r e ) 0 : p a r i t y c h e c k i n g d i s a b l e d 1 : p a r i t y c h e c k i n g e n a b l e d p a r i t y s e l e c t i o n b i t ( p a r s ) 0 : e v e n p a r i t y 1 : o d d p a r i t y s t o p b i t l e n g t h s e l e c t i o n b i t ( s t p s ) 0 : 1 s t o p b i t 1 : 2 s t o p b i t s p 4 5 / t x d 1 p - c h a n n e l o u t p u t d i s a b l e b i t ( p o f f ) 0 : c m o s o u t p u t ( i n o u t p u t m o d e ) 1 : n - c h a n n e l o p e n d r a i n o u t p u t ( i n o u t p u t m o d e ) n o t u s e d ( r e t u r n 1 w h e n r e a d ) b 0 ( s i o 1 s t s : a d d r e s s 0 0 1 9 1 6 ) ( s i o 1 c o n : a d d r e s s 0 0 1 a 1 6 ) ( u a r t c o n : a d d r e s s 0 0 1 b 1 6 )
51 3803/3804 group single-chip 8-bit cmos microcomputer mitsubishi microcomputers 2. notes when selecting clock asynchronous serial i/o 2.1 stop of transmission operation l note clear the transmit enable bit to 0 (transmit disabled). l reason since transmission is not stopped and the transmission circuit is not initialized even if only the serial i/o enable bit is cleared to 0 (serial i/o disabled), the internal transmission is running (in this case, since pins txd, rxd, s clk , and s rdy function as i/o ports, the transmission data is not output). when data is written to the transmit buffer register in this state, data starts to be shifted to the transmit shift register. when the serial i/o enable bit is set to 1 at this time, the data during internally shifting is output to the txd pin and an operation failure occurs. 2.2 stop of receive operation l note clear the receive enable bit to 0 (receive disabled). 2.3 stop of transmit/receive operation l note 1 (only transmission operation is stopped) clear the transmit enable bit to 0 (transmit disabled). l reason since transmission is not stopped and the transmission circuit is not initialized even if only the serial i/o enable bit is cleared to 0 (serial i/o disabled), the internal transmission is running (in this case, since pins txd, rxd, s clk , and s rdy function as i/o ports, the transmission data is not output). when data is written to the transmit buffer register in this state, data starts to be shifted to the transmit shift register. when the serial i/o enable bit is set to 1 at this time, the data during internally shifting is output to the txd pin and an operation failure occurs. l note 2 (only receive operation is stopped) clear the receive enable bit to 0 (receive disabled). n notes concerning serial i/o1 1. notes when selecting clock synchronous serial i/o 1.1 stop of transmission operation l note clear the serial i/o enable bit and the transmit enable bit to 0 (serial i/o and transmit disabled). l reason since transmission is not stopped and the transmission circuit is not initialized even if only the serial i/o enable bit is cleared to 0 (serial i/o disabled), the internal transmission is running (in this case, since pins txd, rxd, s clk , and s rdy function as i/o ports, the transmission data is not output). when data is written to the transmit buffer register in this state, data starts to be shifted to the transmit shift register. when the serial i/o enable bit is set to 1 at this time, the data during internally shifting is output to the txd pin and an operation failure occurs. 1.2 stop of receive operation l note clear the receive enable bit to 0 (receive disabled), or clear the serial i/o enable bit to 0 (serial i/o disabled). 1.3 stop of transmit/receive operation l note clear both the transmit enable bit and receive enable bit to 0 (transmit and receive disabled). (when data is transmitted and received in the clock synchronous serial i/o mode, any one of data transmission and reception can- not be stopped.) l reason in the clock synchronous serial i/o mode, the same clock is used for transmission and reception. if any one of transmission and re- ception is disabled, a bit error occurs because transmission and reception cannot be synchronized. in this mode, the clock circuit of the transmission circuit also oper- ates for data reception. accordingly, the transmission circuit does not stop by clearing only the transmit enable bit to 0 (transmit disabled). also, the transmission circuit is not initialized by clear- ing the serial i/o enable bit to 0 (serial i/o disabled) (refer to 1.1 ).
52 3803/3804 group single-chip 8-bit cmos microcomputer mitsubishi microcomputers 3. s rdy output of reception side l note when signals are output from the s rdy pin on the reception side by using an external clock in the clock synchronous serial i/o mode, set all of the receive enable bit, the s rdy output enable bit, and the transmit enable bit to 1 (transmit enabled). 4. setting serial i/o control register again l note set the serial i/o control register again after the transmission and the reception circuits are reset by clearing both the transmit en- able bit and the receive enable bit to 0. 5. data transmission control with referring to transmit shift register completion flag l note the transmit shift register completion flag changes from 1 to 0 with a delay of 0.5 to 1.5 shift clocks. when data transmission is controlled with referring to the flag after writing the data to the transmit buffer register, note the delay. 6. transmission control when external clock is selected l note when an external clock is used as the synchronous clock for data transmission, set the transmit enable bit to 1 at h of the s clk input level. also, write data to the transmit buffer register at h of the s clk input level. 7. transmit interrupt request when transmit enable bit is set l note when the transmit enable bit is set to 1, the transmit buffer empty flag and the transmit shift register shift completion flag are also set to 1. therefore, regardless of selecting which timing for the generating of transmit interrupts, the interrupt request is gener- ated and the transmit interrupt request bit is set at this point. to use transmit interrupts, first set the transmit enable bit, then clear the transmit interrupt request bit to 0 and set the transmit interrupt enable bit to enabled. clear both the transmit enable bit (te) and the receive enable bit (re) to 0 set the bits 0 to 3 and bit 6 of the serial i/o control register set both the transmit enable bit (te) and the receive enable bit (re), or one of them to 1 can be set with the ldm instruction at the same time
53 3803/3804 group single-chip 8-bit cmos microcomputer mitsubishi microcomputers serial i/o2 the serial i/o2 function can be used only for clock synchronous serial i/o. for clock synchronous serial i/o2, the transmitter and the receiver must use the same clock. if the internal clock is used, transfer is started by a write signal to the serial i/o2 register. [serial i/o2 control register (sio2con)] 001d 16 the serial i/o2 control register contains eight bits which control various serial i/o functions. fig. 43 structure of serial i/o2 control register fig. 44 block diagram of serial i/o2 s e r i a l i / o 2 c o n t r o l r e g i s t e r ( s i o 2 c o n : a d d r e s s 0 0 1 d 1 6 ) b 7 i n t e r n a l s y n c h r o n o u s c l o c k s e l e c t i o n b i t s 0 0 0 : f ( x i n ) / 8 ( f ( x c i n ) / 8 i n l o w - s p e e d m o d e ) 0 0 1 : f ( x i n ) / 1 6 ( f ( x c i n ) / 1 6 i n l o w - s p e e d m o d e ) 0 1 0 : f ( x i n ) / 3 2 ( f ( x c i n ) / 3 2 i n l o w - s p e e d m o d e ) 0 1 1 : f ( x i n ) / 6 4 ( f ( x c i n ) / 6 4 i n l o w - s p e e d m o d e ) 1 1 0 : f ( x i n ) / 1 2 8 ( f ( x c i n ) / 1 2 8 i n l o w - s p e e d m o d e ) 1 1 1 : f ( x i n ) / 2 5 6 ( f ( x c i n ) / 2 5 6 i n l o w - s p e e d m o d e ) s e r i a l i / o 2 p o r t s e l e c t i o n b i t 0 : i / o p o r t 1 : s o u t 2 , s c l k 2 s i g n a l o u t p u t s r d y 2 o u t p u t e n a b l e b i t 0 : i / o p o r t 1 : s r d y 2 s i g n a l o u t p u t t r a n s f e r d i r e c t i o n s e l e c t i o n b i t 0 : l s b f i r s t 1 : m s b f i r s t s e r i a l i / o 2 s y n c h r o n o u s c l o c k s e l e c t i o n b i t 0 : e x t e r n a l c l o c k 1 : i n t e r n a l c l o c k p 5 1 / s o u t 2 p - c h a n n e l o u t p u t d i s a b l e b i t 0 : c m o s o u t p u t ( i n o u t p u t m o d e ) 1 : n - c h a n n e l o p e n d r a i n o u t p u t ( i n o u t p u t m o d e ) b 0 b 2 b 1 b 0 1 0 0 1 0 1 s r d y 2 s c l k 2 0 1 1 / 8 1 / 1 6 1 / 3 2 1 / 6 4 1 / 1 2 8 1 / 2 5 6 d a t a b u s s e r i a l i / o 2 i n t e r r u p t r e q u e s t s e r i a l i / o 2 p o r t s e l e c t i o n b i t s e r i a l i / o c o u n t e r 2 ( 3 ) s e r i a l i / o s h i f t r e g i s t e r 2 ( 8 ) s y n c h r o n i z a t i o n c i r c u i t s e r i a l i / o 2 p o r t s e l e c t i o n b i t s e r i a l i / o 2 s y n c h r o n o u s c l o c k s e l e c t i o n b i t s r d y 2 o u t p u t e n a b l e b i t e x t e r n a l c l o c k i n t e r n a l s y n c h r o n o u s c l o c k s e l e c t i o n b i t s d i v i d e r p 5 2 / s c l k 2 p 5 1 / s o u t 2 p 5 0 / s i n 2 p 5 2 l a t c h p 5 1 l a t c h p 5 3 l a t c h p 5 3 / s r d y 2 f ( x i n ) ( f ( x c i n ) i n l o w - s p e e d m o d e )
54 3803/3804 group single-chip 8-bit cmos microcomputer mitsubishi microcomputers fig. 45 timing of serial i/o2 d 7 d 0 d 1 d 2 d 3 d 4 d 5 d 6 t r a n s f e r c l o c k ( n o t e 1 ) s e r i a l i / o 2 o u t p u t s o u t 2 s e r i a l i / o 2 i n p u t s i n 2 r e c e i v e e n a b l e s i g n a l s r d y 2 s e r i a l i / o 2 r e g i s t e r w r i t e s i g n a l ( n o t e 2 ) s e r i a l i / o 2 i n t e r r u p t r e q u e s t b i t s e t 1 : w h e n t h e i n t e r n a l c l o c k i s s e l e c t e d a s t h e t r a n s f e r c l o c k , t h e d i v i d e r a t i o o f f ( x i n ) , o r f ( x c i n ) i n l o w - s p e e d m o d e , c a n b e s e l e c t e d b y s e t t i n g b i t s 0 t o 2 o f t h e s e r i a l i / o 2 c o n t r o l r e g i s t e r . 2 : w h e n t h e i n t e r n a l c l o c k i s s e l e c t e d a s t h e t r a n s f e r c l o c k , t h e s o u t 2 p i n g o e s t o h i g h i m p e d a n c e a f t e r t r a n s f e r c o m p l e t i o n . n o t e s
55 3803/3804 group single-chip 8-bit cmos microcomputer mitsubishi microcomputers serial i/o3 serial i/o3 can be used as either clock synchronous or asynchro- nous (uart) serial i/o. a dedicated timer is also provided for baud rate generation. (1) clock synchronous serial i/o mode clock synchronous serial i/o3 mode can be selected by setting the serial i/o3 mode selection bit of the serial i/o3 control register (bit 6 of address 0032 16 ) to 1. for clock synchronous serial i/o, the transmitter and the receiver must use the same clock. if an internal clock is used, transfer is started by a write signal to the transmit/receive buffer register. fig. 46 block diagram of clock synchronous serial i/o3 fig. 47 operation of clock synchronous serial i/o3 1 / 4 1 / 4 f / f p 3 6 / s c l k 3 s e r i a l i / o 3 s t a t u s r e g i s t e r s e r i a l i / o 3 c o n t r o l r e g i s t e r p 3 7 / s r d y 3 p 3 4 / r x d 3 p 3 5 / t x d 3 r e c e i v e b u f f e r r e g i s t e r 3 a d d r e s s 0 0 3 0 1 6 r e c e i v e s h i f t r e g i s t e r 3 r e c e i v e b u f f e r f u l l f l a g ( r b f ) r e c e i v e i n t e r r u p t r e q u e s t ( r i ) c l o c k c o n t r o l c i r c u i t s h i f t c l o c k s e r i a l i / o 3 s y n c h r o n o u s c l o c k s e l e c t i o n b i t f r e q u e n c y d i v i s i o n r a t i o 1 / ( n + 1 ) b a u d r a t e g e n e r a t o r 3 a d d r e s s 0 0 2 f 1 6 b r g c o u n t s o u r c e s e l e c t i o n b i t c l o c k c o n t r o l c i r c u i t f a l l i n g - e d g e d e t e c t o r t r a n s m i t b u f f e r r e g i s t e r 3 d a t a b u s a d d r e s s 0 0 3 0 1 6 s h i f t c l o c k t r a n s m i t s h i f t c o m p l e t i o n f l a g ( t s c ) t r a n s m i t b u f f e r e m p t y f l a g ( t b e ) t r a n s m i t i n t e r r u p t r e q u e s t ( t i ) t r a n s m i t i n t e r r u p t s o u r c e s e l e c t i o n b i t a d d r e s s 0 0 3 1 1 6 d a t a b u s a d d r e s s 0 0 3 2 1 6 t r a n s m i t s h i f t r e g i s t e r 3 f ( x i n ) ( f ( x c i n ) i n l o w - s p e e d m o d e ) d 7 d 7 d 0 d 1 d 2 d 3 d 4 d 5 d 6 d 0 d 1 d 2 d 3 d 4 d 5 d 6 r b f = 1 t s c = 1 t b e = 0 t b e = 1 t s c = 0 t r a n s f e r s h i f t c l o c k ( 1 / 2 t o 1 / 2 0 4 8 o f t h e i n t e r n a l c l o c k , o r a n e x t e r n a l c l o c k ) s e r i a l o u t p u t t x d 3 s e r i a l i n p u t r x d 3 w r i t e p u l s e t o r e c e i v e / t r a n s m i t b u f f e r r e g i s t e r ( a d d r e s s 0 0 3 0 1 6 ) o v e r r u n e r r o r ( o e ) d e t e c t i o n n o t e s 1 : a s t h e t r a n s m i t i n t e r r u p t ( t i ) , w h i c h c a n b e s e l e c t e d , e i t h e r w h e n t h e t r a n s m i t b u f f e r h a s e m p t i e d ( t b e = 1 ) o r a f t e r t h e t r a n s m i t s h i f t o p e r a t i o n h a s e n d e d ( t s c = 1 ) , b y s e t t i n g t h e t r a n s m i t i n t e r r u p t s o u r c e s e l e c t i o n b i t ( t i c ) o f t h e s e r i a l i / o 3 c o n t r o l r e g i s t e r . 2 : i f d a t a i s w r i t t e n t o t h e t r a n s m i t b u f f e r r e g i s t e r w h e n t s c = 0 , t h e t r a n s m i t c l o c k i s g e n e r a t e d c o n t i n u o u s l y a n d s e r i a l d a t a i s o u t p u t c o n t i n u o u s l y f r o m t h e t x d p i n . 3 : t h e r e c e i v e i n t e r r u p t ( r i ) i s s e t w h e n t h e r e c e i v e b u f f e r f u l l f l a g ( r b f ) b e c o m e s 1 . r e c e i v e e n a b l e s i g n a l s r d y 3
56 3803/3804 group single-chip 8-bit cmos microcomputer mitsubishi microcomputers (2) asynchronous serial i/o (uart) mode clock asynchronous serial i/o mode (uart) can be selected by clearing the serial i/o3 mode selection bit of the serial i/o3 control register to 0. eight serial data transfer formats can be selected, and the transfer formats used by a transmitter and receiver must be identical. the transmit and receive shift registers each have a buffer, but the two buffers have the same address in a memory. since the shift register cannot be written to or read from directly, transmit data is written to the transmit buffer register, and receive data is read from the receive buffer register. the transmit buffer register can also hold the next data to be transmitted, and the receive buffer register can hold a character while the next character is being received. fig. 48 block diagram of uart serial i/o3 fig. 49 operation of uart serial i/o3 f ( x i n ) 1 / 4 o e p ef e 1 / 1 6 1 / 1 6 d a t a b u s r e c e i v e b u f f e r r e g i s t e r 3 a d d r e s s 0 0 3 0 1 6 r e c e i v e s h i f t r e g i s t e r 3 r e c e i v e b u f f e r f u l l f l a g ( r b f ) r e c e i v e i n t e r r u p t r e q u e s t ( r i ) b a u d r a t e g e n e r a t o r 3 f r e q u e n c y d i v i s i o n r a t i o 1 / ( n + 1 ) a d d r e s s 0 0 2 f 1 6 s t / s p / p a g e n e r a t o r t r a n s m i t b u f f e r r e g i s t e r 3 d a t a b u s t r a n s m i t s h i f t r e g i s t e r 3 a d d r e s s 0 0 3 0 1 6 t r a n s m i t s h i f t c o m p l e t i o n f l a g ( t s c ) t r a n s m i t b u f f e r e m p t y f l a g ( t b e ) t r a n s m i t i n t e r r u p t r e q u e s t ( t i ) a d d r e s s 0 0 3 1 1 6 s t d e t e c t o r s p d e t e c t o r u a r t 3 c o n t r o l r e g i s t e r a d d r e s s 0 0 3 3 1 6 c h a r a c t e r l e n g t h s e l e c t i o n b i t a d d r e s s 0 0 3 2 1 6 b r g c o u n t s o u r c e s e l e c t i o n b i t t r a n s m i t i n t e r r u p t s o u r c e s e l e c t i o n b i t s e r i a l i / o 3 s y n c h r o n o u s c l o c k s e l e c t i o n b i t c l o c k c o n t r o l c i r c u i t c h a r a c t e r l e n g t h s e l e c t i o n b i t 7 b i t s 8 b i t s s e r i a l i / o 3 c o n t r o l r e g i s t e r p 3 6 / s c l k 3 s e r i a l i / o 3 s t a t u s r e g i s t e r p 3 4 / r x d 3 p 3 5 / t x d 3 ( f ( x c i n ) i n l o w - s p e e d m o d e ) t s c = 0 t b e = 1 r b f = 0 t b e = 0t b e = 0 r b f = 1 r b f = 1 s t d 0 d 1 s p d 0 d 1 s t s p t b e = 1 t s c = 1 s t d 0 d 1 s p d 0 d 1 s t s p transmit or receive cloc k transmit buffer write signal g e n e r a t e d a t 2 n d b i t i n 2 - s t o p - b i t m o d e 1 s t a r t b i t 7 o r 8 d a t a b i t 1 o r 0 p a r i t y b i t 1 o r 2 s t o p b i t ( s ) 1 : e r r o r f l a g d e t e c t i o n o c c u r s a t t h e s a m e t i m e t h a t t h e r b f f l a g b e c o m e s 1 ( a t 1 s t s t o p b i t , d u r i n g r e c e p t i o n ) . 2 : a s t h e t r a n s m i t i n t e r r u p t ( t i ) , w h e n e i t h e r t h e t b e o r t s c f l a g b e c o m e s 1 , c a n b e s e l e c t e d t o o c c u r d e p e n d i n g o n t h e s e t t i n g o f t h e t r a n s m i t i n t e r r u p t s o u r c e s e l e c t i o n b i t ( t i c ) o f t h e s e r i a l i / o 3 c o n t r o l r e g i s t e r . 3 : t h e r e c e i v e i n t e r r u p t ( r i ) i s s e t w h e n t h e r b f f l a g b e c o m e s 1 . 4 : a f t e r d a t a i s w r i t t e n t o t h e t r a n s m i t b u f f e r w h e n t s c = 1 , 0 . 5 t o 1 . 5 c y c l e s o f t h e d a t a s h i f t c y c l e a r e n e c e s s a r y u n t i l c h a n g i n g t o t s c = 0 . n o t e s ] ] serial output t x d 3 serial input r x d 3 receive buffer read signal
57 3803/3804 group single-chip 8-bit cmos microcomputer mitsubishi microcomputers [serial i/o3 control register (sio3con)] 0032 16 the serial i/o3 control register consists of eight control bits for the serial i/o function. [uart3 control register (uart3con)] 0033 16 the uart control register consists of four control bits (bits 0 to 3) which are valid when asynchronous serial i/o is selected and set the data format of an data transfer, and one bit (bit 4) which is al- ways valid and sets the output structure of the p3 5 /t x d 3 pin. [serial i/o3 status register (sio3sts)] 0031 16 the read-only serial i/o3 status register consists of seven flags (bits 0 to 6) which indicate the operating status of the serial i/o3 function and various errors. three of the flags (bits 4 to 6) are valid only in uart mode. the receive buffer full flag (bit 1) is cleared to 0 when the receive buffer register is read. if there is an error, it is detected at the same time that data is transferred from the receive shift register to the receive buffer reg- ister, and the receive buffer full flag is set. a write to the serial i/o3 status register clears all the error flags oe, pe, fe, and se (bit 3 to bit 6, respectively). writing 0 to the serial i/o3 enable bit sioe (bit 7 of the serial i/o3 control register) also clears all the status flags, including the error flags. bits 0 to 6 of the serial i/o3 status register are initialized to 0 at reset, but if the transmit enable bit (bit 4) of the serial i/o3 control register has been set to 1, the transmit shift completion flag (bit 2) and the transmit buffer empty flag (bit 0) become 1. [transmit buffer register 3/receive buffer register 3 (tb3/rb3)] 0030 16 the transmit buffer register 3 and the receive buffer register 3 are located at the same address. the transmit buffer is write-only and the receive buffer is read-only. if a character bit length is 7 bits, the msb of data stored in the receive buffer is 0. [baud rate generator 3 (brg3)] 002f 16 the baud rate generator determines the baud rate for serial trans- fer. the baud rate generator divides the frequency of the count source by 1/(n + 1), where n is the value written to the baud rate genera- tor.
58 3803/3804 group single-chip 8-bit cmos microcomputer mitsubishi microcomputers fig. 50 structure of serial i/o3 control registers b 7 b 7 t r a n s m i t b u f f e r e m p t y f l a g ( t b e ) 0 : b u f f e r f u l l 1 : b u f f e r e m p t y r e c e i v e b u f f e r f u l l f l a g ( r b f ) 0 : b u f f e r e m p t y 1 : b u f f e r f u l l t r a n s m i t s h i f t c o m p l e t i o n f l a g ( t s c ) 0 : t r a n s m i t s h i f t i n p r o g r e s s 1 : t r a n s m i t s h i f t c o m p l e t e d o v e r r u n e r r o r f l a g ( o e ) 0 : n o e r r o r 1 : o v e r r u n e r r o r p a r i t y e r r o r f l a g ( p e ) 0 : n o e r r o r 1 : p a r i t y e r r o r f r a m i n g e r r o r f l a g ( f e ) 0 : n o e r r o r 1 : f r a m i n g e r r o r s u m m i n g e r r o r f l a g ( s e ) 0 : ( o e ) u ( p e ) u ( f e ) = 0 1 : ( o e ) u ( p e ) u ( f e ) = 1 n o t u s e d ( r e t u r n s 1 w h e n r e a d ) s e r i a l i / o 3 s t a t u s r e g i s t e r s e r i a l i / o 3 c o n t r o l r e g i s t e r b 0 b 0 b r g c o u n t s o u r c e s e l e c t i o n b i t ( c s s ) 0 : f ( x i n ) ( f ( x c i n ) i n l o w - s p e e d m o d e ) 1 : f ( x i n ) / 4 ( f ( x c i n ) / 4 i n l o w - s p e e d m o d e ) s e r i a l i / o 3 s y n c h r o n o u s c l o c k s e l e c t i o n b i t ( s c s ) 0 : b r g o u t p u t d i v i d e d b y 4 w h e n c l o c k s y n c h r o n o u s s e r i a l i / o i s s e l e c t e d , b r g o u t p u t d i v i d e d b y 1 6 w h e n u a r t i s s e l e c t e d . 1 : e x t e r n a l c l o c k i n p u t w h e n c l o c k s y n c h r o n o u s s e r i a l i / o i s s e l e c t e d , e x t e r n a l c l o c k i n p u t d i v i d e d b y 1 6 w h e n u a r t i s s e l e c t e d . s r d y 3 o u t p u t e n a b l e b i t ( s r d y ) 0 : p 3 7 p i n o p e r a t e s a s n o r m a l i / o p i n 1 : p 3 7 p i n o p e r a t e s a s s r d y 3 o u t p u t p i n t r a n s m i t i n t e r r u p t s o u r c e s e l e c t i o n b i t ( t i c ) 0 : i n t e r r u p t w h e n t r a n s m i t b u f f e r h a s e m p t i e d 1 : i n t e r r u p t w h e n t r a n s m i t s h i f t o p e r a t i o n i s c o m p l e t e d t r a n s m i t e n a b l e b i t ( t e ) 0 : t r a n s m i t d i s a b l e d 1 : t r a n s m i t e n a b l e d r e c e i v e e n a b l e b i t ( r e ) 0 : r e c e i v e d i s a b l e d 1 : r e c e i v e e n a b l e d s e r i a l i / o 3 m o d e s e l e c t i o n b i t ( s i o m ) 0 : c l o c k a s y n c h r o n o u s ( u a r t ) s e r i a l i / o 1 : c l o c k s y n c h r o n o u s s e r i a l i / o s e r i a l i / o 3 e n a b l e b i t ( s i o e ) 0 : s e r i a l i / o d i s a b l e d ( p i n s p 3 4 t o p 3 7 o p e r a t e a s n o r m a l i / o p i n s ) 1 : s e r i a l i / o e n a b l e d ( p i n s p 3 4 t o p 3 7 o p e r a t e a s s e r i a l i / o p i n s ) b 7 u a r t 3 c o n t r o l r e g i s t e r c h a r a c t e r l e n g t h s e l e c t i o n b i t ( c h a s ) 0 : 8 b i t s 1 : 7 b i t s p a r i t y e n a b l e b i t ( p a r e ) 0 : p a r i t y c h e c k i n g d i s a b l e d 1 : p a r i t y c h e c k i n g e n a b l e d p a r i t y s e l e c t i o n b i t ( p a r s ) 0 : e v e n p a r i t y 1 : o d d p a r i t y s t o p b i t l e n g t h s e l e c t i o n b i t ( s t p s ) 0 : 1 s t o p b i t 1 : 2 s t o p b i t s p 3 5 / t x d 3 p - c h a n n e l o u t p u t d i s a b l e b i t ( p o f f ) 0 : c m o s o u t p u t ( i n o u t p u t m o d e ) 1 : n - c h a n n e l o p e n d r a i n o u t p u t ( i n o u t p u t m o d e ) n o t u s e d ( r e t u r n 1 w h e n r e a d ) b 0 ( s i o 3 s t s : a d d r e s s 0 0 3 1 1 6 ) ( s i o 3 c o n : a d d r e s s 0 0 3 2 1 6 ) ( u a r t 3 c o n : a d d r e s s 0 0 3 3 1 6 )
59 3803/3804 group single-chip 8-bit cmos microcomputer mitsubishi microcomputers 2. notes when selecting clock asynchronous serial i/o 2.1 stop of transmission operation l note clear the transmit enable bit to 0 (transmit disabled). l reason since transmission is not stopped and the transmission circuit is not initialized even if only the serial i/o enable bit is cleared to 0 (serial i/o disabled), the internal transmission is running (in this case, since pins txd, rxd, s clk , and s rdy function as i/o ports, the transmission data is not output). when data is written to the transmit buffer register in this state, data starts to be shifted to the transmit shift register. when the serial i/o enable bit is set to 1 at this time, the data during internally shifting is output to the txd pin and an operation failure occurs. 2.2 stop of receive operation l note clear the receive enable bit to 0 (receive disabled). 2.3 stop of transmit/receive operation l note 1 (only transmission operation is stopped) clear the transmit enable bit to 0 (transmit disabled). l reason since transmission is not stopped and the transmission circuit is not initialized even if only the serial i/o enable bit is cleared to 0 (serial i/o disabled), the internal transmission is running (in this case, since pins txd, rxd, s clk , and s rdy function as i/o ports, the transmission data is not output). when data is written to the transmit buffer register in this state, data starts to be shifted to the transmit shift register. when the serial i/o enable bit is set to 1 at this time, the data during internally shifting is output to the txd pin and an operation failure occurs. l note 2 (only receive operation is stopped) clear the receive enable bit to 0 (receive disabled). n notes concerning serial i/o3 1. notes when selecting clock synchronous serial i/o 1.1 stop of transmission operation l note clear the serial i/o enable bit and the transmit enable bit to 0 (serial i/o and transmit disabled). l reason since transmission is not stopped and the transmission circuit is not initialized even if only the serial i/o enable bit is cleared to 0 (serial i/o disabled), the internal transmission is running (in this case, since pins txd, rxd, s clk , and s rdy function as i/o ports, the transmission data is not output). when data is written to the transmit buffer register in this state, data starts to be shifted to the transmit shift register. when the serial i/o enable bit is set to 1 at this time, the data during internally shifting is output to the txd pin and an operation failure occurs. 1.2 stop of receive operation l note clear the receive enable bit to 0 (receive disabled), or clear the serial i/o enable bit to 0 (serial i/o disabled). 1.3 stop of transmit/receive operation l note clear both the transmit enable bit and receive enable bit to 0 (transmit and receive disabled). (when data is transmitted and received in the clock synchronous serial i/o mode, any one of data transmission and reception can- not be stopped.) l reason in the clock synchronous serial i/o mode, the same clock is used for transmission and reception. if any one of transmission and re- ception is disabled, a bit error occurs because transmission and reception cannot be synchronized. in this mode, the clock circuit of the transmission circuit also oper- ates for data reception. accordingly, the transmission circuit does not stop by clearing only the transmit enable bit to 0 (transmit disabled). also, the transmission circuit is not initialized by clear- ing the serial i/o enable bit to 0 (serial i/o disabled) (refer to 1.1 ).
60 3803/3804 group single-chip 8-bit cmos microcomputer mitsubishi microcomputers 3. s rdy output of reception side l note when signals are output from the s rdy pin on the reception side by using an external clock in the clock synchronous serial i/o mode, set all of the receive enable bit, the s rdy output enable bit, and the transmit enable bit to 1 (transmit enabled). 4. setting serial i/o control register again l note set the serial i/o control register again after the transmission and the reception circuits are reset by clearing both the transmit en- able bit and the receive enable bit to 0. 5. data transmission control with referring to transmit shift register completion flag l note the transmit shift register completion flag changes from 1 to 0 with a delay of 0.5 to 1.5 shift clocks. when data transmission is controlled with referring to the flag after writing the data to the transmit buffer register, note the delay. 6. transmission control when external clock is selected l note when an external clock is used as the synchronous clock for data transmission, set the transmit enable bit to 1 at h of the s clk input level. also, write data to the transmit buffer register at h of the s clk input level. 7. transmit interrupt request when transmit enable bit is set l note when the transmit enable bit is set to 1, the transmit buffer empty flag and the transmit shift register shift completion flag are also set to 1. therefore, regardless of selecting which timing for the generating of transmit interrupts, the interrupt request is gener- ated and the transmit interrupt request bit is set at this point. to use transmit interrupts, first set the transmit enable bit, then clear the transmit interrupt request bit to 0 and set the transmit interrupt enable bit to enabled. clear both the transmit enable bit (te) and the receive enable bit (re) to 0 set the bits 0 to 3 and bit 6 of the serial i/o control register set both the transmit enable bit (te) and the receive enable bit (re), or one of them to 1 can be set with the ldm instruction at the same time
61 3803/3804 group single-chip 8-bit cmos microcomputer mitsubishi microcomputers pulse width modulation (pwm) the 3803/3804 group has pwm functions with an 8-bit resolution, based on a signal that is the clock input x in or that clock input di- vided by 2 or the clock input x cin or that clock input divided by 2 in low-speed mode. data setting the pwm output pin also functions as port p5 6 . set the pwm pe- riod by the pwm prescaler, and set the h term of output pulse by the pwm register. if the value in the pwm prescaler is n and the value in the pwm register is m (where n = 0 to 255 and m = 0 to 255) : pwm period = 255 5 (n+1) / f(x in ) = 31.875 5 (n+1) m s (when f(x in ) = 8 mhz) output pulse h term = pwm period 5 m / 255 = 0.125 5 (n+1) 5 m m s (when f(x in ) = 8 mhz) fig. 51 timing of pwm period fig. 52 block diagram of pwm function pwm operation when bit 0 (pwm enable bit) of the pwm control register is set to 1, operation starts by initializing the pwm output circuit, and pulses are output starting at an h. if the pwm register or pwm prescaler is updated during pwm output, the pulses will change in the cycle after the one in which the change was made. 3 1 . 8 7 5 5 m 5 ( n + 1 ) 2 5 5 m s t = [ 3 1 . 8 7 5 5 ( n + 1 ) ] m s p w m o u t p u t m : c o n t e n t s o f p w m r e g i s t e r n : c o n t e n t s o f p w m p r e s c a l e r t : p w m p e r i o d ( w h e n f ( x i n ) = 8 m h z , c o u n t s o u r c e i s f ( x i n ) ) d a t a b u s c o u n t s o u r c e s e l e c t i o n b i t 0 1 p w m p r e s c a l e r p r e - l a t c h p w m r e g i s t e r p r e - l a t c h p w m p r e s c a l e r l a t c h p w m r e g i s t e r l a t c h t r a n s f e r c o n t r o l c i r c u i t p w m r e g i s t e r 1 / 2 x i n o r x c i n p o r t p 5 6 l a t c h p w m e n a b l e b i t p o r t p 5 6 p w m p r e s c a l e r
62 3803/3804 group single-chip 8-bit cmos microcomputer mitsubishi microcomputers fig. 53 structure of pwm control register fig. 54 pwm output timing when pwm register or pwm prescaler is changed p w m c o n t r o l r e g i s t e r ( p w m c o n : a d d r e s s 0 0 2b 1 6 ) p w m f u n c t i o n e n a b l e b i t c o u n t s o u r c e s e l e c t i o n b i t n o t u s e d ( r e t u r n 0 w h e n r e a d ) b 7 b 0 0 : p w m d i s a b l e d 1 : p w m e n a b l e d 0 : f ( x i n ) 1 : f ( x i n ) / 2 abc b t c t 2 = p w m o u t p u t p w m r e g i s t e r w r i t e s i g n a l pwm prescaler write signal ( c h a n g e s h t e r m f r o m a t o b . ) ( c h a n g e s p w m p e r i o d f r o m t t o t 2 . ) w h e n t h e c o n t e n t s o f t h e p w m r e g i s t e r o r p w m p r e s c a l e r h a v e c h a n g e d , t h e p w m o u t p u t w i l l c h a n g e f r o m t h e n e x t p e r i o d a f t e r t h e c h a n g e . t t t 2
63 3803/3804 group single-chip 8-bit cmos microcomputer mitsubishi microcomputers a-d converter [a-d conversion register 1, 2 (ad1, ad2)] 0035 16 , 0038 16 the a-d conversion register is a read-only register that stores the result of an a-d conversion. when reading this register during an a-d conversion, the previous conversion result is read. bit 7 of the a-d conversion register 2 is the conversion mode se- lection bit. when this bit is set to 0, the a-d converter becomes the 10-bit a-d mode. when this bit is set to 1, that becomes the 8-bit a-d mode. the conversion result of the 8-bit a-d mode is stored in the a-d conversion register 1. as for 10-bit a-d mode, not only 10-bit reading but also only high-order 8-bit reading of conversion result can be performed by selecting the reading pro- cedure of the a-d conversion registers 1, 2 after a-d conversion is completed (in figure 56). as for 10-bit a-d mode, the 8-bit reading inclined to msb is per- formed when reading the a-d converter register 1 after a-d conversion is started; and when the a-d converter register 1 is read after reading the a-d converter register 2, the 8-bit reading inclined to lsb is performed. [ad/da control register (adcon)] 0034 16 the ad/da control register controls the a-d conversion process. bits 0 to 2 and bit 4 select a specific analog input pin. bit 3 signals the completion of an a-d conversion. the value of this bit remains at 0 during an a-d conversion, and changes to 1 when an a-d conversion ends. writing 0 to this bit starts the a-d conversion. comparison voltage generator the comparison voltage generator divides the voltage between v ref and av ss into 1024, and that outputs the comparison voltage in the 10-bit a-d mode (256 division in 8-bit a-d mode). the a-d converter successively compares the comparison voltage v ref in each mode, dividing the v ref voltage (see below), with the input voltage. ? 10-bit a-d mode (10-bit reading) v ref = 5 n (n = 0C1023) ? 10-bit a-d mode (8-bit reading) v ref = 5 n (n = 0C255) ? 8-bit a-d mode v ref = 5 (nC0.5) (n = 1C255) =0 (n = 0) fig. 55 structure of ad/da control register channel selector the channel selector selects one of ports p6 7 /an 7 to p6 0 /an 0 or p0 7 /an 15 to p0 0 /an 8 , and inputs the voltage to the comparator. comparator and control circuit the comparator and control circuit compares an analog input volt- age with the comparison voltage, and then stores the result in the a-d conversion registers 1, 2. when an a-d conversion is com- pleted, the control circuit sets the ad conversion completion bit and the ad interrupt request bit to 1. note that because the comparator consists of a capacitor cou- pling, set f(x in ) to 500 khz or more during an a-d conversion. v ref 256 v ref 256 fig. 56 structure of 10-bit a-d mode reading v ref 1024 a d / d a c o n t r o l r e g i s t e r ( a d c o n : a d d r e s s 0 0 3 4 1 6 ) a n a l o g i n p u t p i n s e l e c t i o n b i t s 1 0 0 0 : p 6 0 / a n 0 o r p 0 0 / a n 8 0 0 1 : p 6 1 / a n 1 o r p 0 1 / a n 9 0 1 0 : p 6 2 / a n 2 o r p 0 2 / a n 1 0 0 1 1 : p 6 3 / a n 3 o r p 0 3 / a n 1 1 1 0 0 : p 6 4 / a n 4 o r p 0 4 / a n 1 2 1 0 1 : p 6 5 / a n 5 o r p 0 5 / a n 1 3 1 1 0 : p 6 6 / a n 6 o r p 0 6 / a n 1 4 1 1 1 : p 6 7 / a n 7 o r p 0 7 / a n 1 5 a d c o n v e r s i o n c o m p l e t i o n b i t 0 : c o n v e r s i o n i n p r o g r e s s 1 : c o n v e r s i o n c o m p l e t e d a n a l o g i n p u t p i n s e l e c t i o n b i t 2 0 : a n 0 t o a n 7 s i d e 1 : a n 8 t o a n 1 5 s i d e n o t u s e d ( r e t u r n s 0 w h e n r e a d ) d a 1 o u t p u t e n a b l e b i t 0 : d a 1 o u t p u t d i s a b l e d 1 : d a 1 o u t p u t e n a b l e d d a 2 o u t p u t e n a b l e b i t 0 : d a 2 o u t p u t d i s a b l e d 1 : d a 2 o u t p u t e n a b l e d b 7 b 0 b 2 b 1 b 0 1 0 - b i t r e a d i n g ( r e a d a d d r e s s 0 0 3 8 1 6 b e f o r e 0 0 3 5 1 6 ) a - d c o n v e r s i o n r e g i s t e r 2 ( a d 2 : a d d r e s s 0 0 3 8 1 6 ) a - d c o n v e r s i o n r e g i s t e r 1 ( a d 1 : a d d r e s s 0 0 3 5 1 6 ) 8 - b i t r e a d i n g ( r e a d o n l y a d d r e s s 0 0 3 5 1 6 ) a - d c o n v e r s i o n r e g i s t e r 1 ( a d 1 : a d d r e s s 0 0 3 5 1 6 ) n o t e : bi t s 2 t o 6 o f a d d r e s s 0 0 3 8 1 6 b e c o m e 0 a t r e a d i n g . b 8 b 7 b 6 b 5 b 4b 3b 2b 1b 0 b 7 b 0 b 9 b 7 b 0 b 9 b 8 b 7 b 6b 5b 4 b 3 b 2 b 7 b 0 0
64 3803/3804 group single-chip 8-bit cmos microcomputer mitsubishi microcomputers fig. 57 block diagram of a-d converter c h a n n e l s e l e c t o r a - d c o n t r o l c i r c u i t a - d c o n v e r s i o n r e g i s t e r 1 r e s i s t o r l a d d e r v r e f a v s s c o m p a r a t o r a d c o n v e r t e r i n t e r r u p t r e q u e s t b 7b 0 4 1 0 p 6 0 / a n 0 p 6 1 / a n 1 p 6 2 / a n 2 p 6 3 / a n 3 p 6 4 / a n 4 d a t a b u s a d / d a c o n t r o l r e g i s t e r a - d c o n v e r s i o n r e g i s t e r 2 ( a d d r e s s 0 0 3 4 1 6 ) ( a d d r e s s 0 0 3 8 1 6 ) ( a d d r e s s 0 0 3 5 1 6 ) p 6 5 / a n 5 p 6 6 / a n 6 p 6 7 / a n 7 p 0 0 / a n 8 p 0 1 / a n 9 p 0 2 / a n 1 0 p 0 3 / a n 1 1 p 0 4 / a n 1 2 p 0 5 / a n 1 3 p 0 6 / a n 1 4 p 0 7 / a n 1 5
65 3803/3804 group single-chip 8-bit cmos microcomputer mitsubishi microcomputers d-a converter the 3803/3804 group has two internal d-a converters (da1 and da2) with 8-bit resolution. the d-a conversion is performed by setting the value in each d-a conversion register. the result of d-a conversion is output from the da 1 or da 2 pin by setting the da output enable bit to 1. when using the d-a converter, the corresponding port direction register bit (p3 0 /da 1 or p3 1 /da 2 ) must be set to 0 (input status). the output analog voltage v is determined by the value n (decimal notation) in the d-a conversion register as follows: v = v ref 5 n/256 (n = 0 to 255) where v ref is the reference voltage. at reset, the d-a conversion registers are cleared to 00 16 , and the da output enable bits are cleared to 0, and the p3 0 /da 1 and p3 1 /da 2 pins become high impedance. the da output does not have buffers. accordingly, connect an ex- ternal buffer when driving a low-impedance load. set v cc to 3.0 v or more when using the d-a converter. fig. 58 block diagram of d-a converter fig. 59 equivalent connection circuit of d-a converter (da1) p 3 0 / d a 1 d - a 1 c o n v e r s i o n r e g i s t e r ( 8 ) r - 2 r r e s i s t o r l a d d e r d a 1 o u t p u t e n a b l e b i t p 3 1 / d a 2 d - a 2 c o n v e r s i o n r e g i s t e r ( 8 ) r - 2 r r e s i s t o r l a d d e r d a 2 o u t p u t e n a b l e b i t d a t a b u s a v s s v r e f 0 1 m s b 0 1 r 2 r r 2 r r 2 r r 2 r r 2 r r 2 r r 2 r2 r l s b 2 r p 3 0 / d a 1 d - a 1 c o n v e r s i o n r e g i s t e r d a 1 o u t p u t e n a b l e b i t
66 3803/3804 group single-chip 8-bit cmos microcomputer mitsubishi microcomputers x in data bus x cin 10 00 01 main clock division ratio selection bits (note) 0 1 1/16 watchdog timer h count source selection bit reset circuit stp instruction disable bit watchdog timer h (8) ff 16 is set when watchdog timer control register is written to. internal reset reset watchdog timer l (8) note: either high-speed, middle-speed or low-speed mode is selected by bits 7 and 6 of the cpu mode register. stp instruction ?f 16 ?is set when watchdog timer control register is written to. reset release time waiting watchdog timer the watchdog timer gives a mean of returning to the reset status when a program cannot run on a normal loop (for example, be- cause of a software run-away). the watchdog timer consists of an 8-bit watchdog timer l and an 8-bit watchdog timer h. watchdog timer initial value watchdog timer l is set to ff 16 and watchdog timer h is set to ff 16 by writing to the watchdog timer control register (address 001e 16 ) or at a reset. any write instruction that causes a write sig- nal can be used, such as the sta, ldm, clb, etc. data can only be written to bits 6 and 7 of the watchdog timer control register. regardless of the value written to bits 0 to 5, the above-mentioned value will be set to each timer. watchdog timer operations the watchdog timer stops at reset and a countdown is started by the writing to the watchdog timer control register. an internal reset occurs when watchdog timer h underflows. the reset is released after its release time. after the release, the program is restarted from the reset vector address. usually, write to the watchdog timer control register by software before an underflow of the watchdog timer h. the watchdog timer does not function if the watchdog timer control register is not written to at least once. fig. 61 structure of watchdog timer control register when bit 6 of the watchdog timer control register is kept at 0, the stp instruction is enabled. when that is executed, both the clock and the watchdog timer stop. count re-starts at the same time as the release of stop mode (note) . the watchdog timer does not stop while a wit instruction is executed. in addition, the stp in- struction is disabled by writing 1 to this bit again. when the stp instruction is executed at this time, it is processed as an undefined instruction, and an internal reset occurs. once a 1 is written to this bit, it cannot be programmed to 0 again. the following shows the period between the write execution to the watchdog timer control register and the underflow of watchdog timer h. bit 7 of the watchdog timer control register is 0: when x cin = 32.768 khz; 32 s when x in = 16 mhz; 65.536 ms bit 7 of the watchdog timer control register is 1: when x cin = 32.768 khz; 125 ms when x in = 16 mhz; 256 m s note: the watchdog timer continues to count even while waiting for a stop release. therefore, make sure that watchdog timer h does not un- derflow during this period. fig. 60 block diagram of watchdog timer b 7 w a t c h d o g t i m e r h ( f o r r e a d - o s t p i n s t r u c t i o n d i s a b l e b i t 0 : s t p i n s t r u c t i o n e n a b l e d 1 : s t p i n s t r u c t i o n d i s a b l e d w a t c h d o g t i m e r h c o u n t s o u 0 : w a t c h d o g t i m e r l u n d e r f l o 1 : f ( x i n ) / 1 6 o r f ( x c i n ) / 1 6 w a t c h d o g t i m e r c o n t r o l r e g i s t e r ( w d t c o n : a d d r e s s 0 0 1 e 1 6 ) b 0
67 3803/3804 group single-chip 8-bit cmos microcomputer mitsubishi microcomputers function in conformity with philips i 2 c-bus standard: 10-bit addressing format 7-bit addressing format high-speed clock mode standard clock mode in conformity with philips i 2 c-bus standard: master transmission master reception slave transmission slave reception 16.1 khz to 400 khz (at f = 4 mhz) table 8 multi-master i 2 c-bus interface functions item format communication mode system clock f = f(x in )/2 (high-speed mode) f = f(x in )/8 (middle-speed mode) multi-master i 2 c-bus interface the 3804 group has the multi-master i 2 c-bus interface. the multi-master i 2 c-bus interface is a serial communications cir- cuit, conforming to the philips i 2 c-bus data transfer format. this interface, offering both arbitration lost detection and a synchro- nous functions, is useful for the multi-master serial communications. figure 62 shows a block diagram of the multi-master i 2 c-bus in- terface and table 8 lists the multi-master i 2 c-bus interface functions. this multi-master i 2 c-bus interface consists of the i 2 c slave ad- dress registers 0 to 2, the i 2 c data shift register, the i 2 c clock control register, the i 2 c control register, the i 2 c status register, the i 2 c start/stop condition control register, the i 2 c special mode control register, the i 2 c special mode status register, and other control circuits. when using the multi-master i 2 c-bus interface, set 1 mhz or more to system clock f . fig. 62 block diagram of multi-master i 2 c-bus interface ] : purchase of mitsubishi electric corporations i 2 c components conveys a license under the philips i 2 c patent rights to use these components an i 2 c system, provided that the system conforms to the i 2 c standard specification as defined by philips. scl clock frequency i 2 c s t a t u s r e g i s t e r b 7b 0 s a d 6s a d 5s a d 4s a d 3s a d 2s a d 1s a d 0r b w b 7b 0 b 7 m s tt r xb bp i n a la a s a d 0l r b b 0 s 1 b b c i r c u i t b 7b 0 a c k a c k b i t f a s t m o d e c c r 4 c c r 3 c c r 2c c r 1c c r 0 s 0 s 2 s 0 d 0 2 s i s i 2 c s t a r t / s t o p c o n d i t i o n c o n t r o l r e g i s t e r s i p s s c 4 s s c 3 s s c 2s s c 1s s c 0 b 7b 0 t i s s t s e l 1 0 b i t s a d a l s b c 2b c 1 b c 0 s 1 d e s 0 s t r b 7b 0 s p c f s 3 p i n 2t i o u ta a s 2a a s 1a a s 0 b 7b 0 s p c f l s 3 d p i n 2 h d p i n 2 i n t o f c lh s l a dt o e n a c k i c o n i 2 c s p e c i a l m o d e c o n t r o l r e g i s t e r i 2 c s p e c i a l m o d e s t a t u s r e g i s t e r i 2 c s l a v e a d d r e s s r e g i s t e r s 0 t o 2 n o i s e e l i m i n a t i o n c i r c u i t a d d r e s s c o m p a r a t o r d a t a c o n t r o l c i r c u i t s y s t e m c l o c k ( f ) i n t e r r u p t g e n e r a t i n g c i r c u i t i n t e r r u p t r e q u e s t s i g n a l ( i 2 c i r q ) b i t c o u n t e r c l o c k c o n t r o l c i r c u i t i n t e r n a l d a t a b u s c l o c k d i v i s i o n a l c i r c u i t i 2 c c l o c k c o n t r o l r e g i s t e r i 2 c c o n t r o l r e g i s t e r s e r i a l c l o c k ( s c l ) i 2 c d a t a s h i f t r e g i s t e r i n t e r r u p t r e q u e s t s i g n a l ( s c l , s d a , i r q ) i n t e r r u p t g e n e r a t i n g c i r c u i t s e r i a l d a t a ( s d a ) n o i s e e l i m i n a t i o n c i r c u i t s 2 d t i m e o u t c o n t r o l c i r c u i t
68 3803/3804 group single-chip 8-bit cmos microcomputer mitsubishi microcomputers [i 2 c data shift register (s0)] 0011 16 the i 2 c data shift register (s0: address 0011 16 ) is an 8-bit shift register to store receive data and write transmit data. when transmit data is written into this register, it is transferred to the outside from bit 7 in synchronization with the scl, and each time one-bit data is output, the data of this register are shifted by one bit to the left. when data is received, it is input to this register from bit 0 in synchronization with the scl, and each time one-bit data is input, the data of this register are shifted by one bit to the left. the minimum 2 cycles of system clock f are required from the rising of the scl until input to this register. the i 2 c data shift register is in a write enable status only when the i 2 c-bus interface enable bit (es0 bit) of the i 2 c control register (s1d: address 0014 16 ) is 1. the bit counter is reset by a write in- struction to the i 2 c data shift register. when both the es0 bit and the mst bit of the i 2 c status register (s1: address 0013 16 ) are 1, the scl is output by a write instruction to the i 2 c data shift regis- ter. reading data from the i 2 c data shift register is always enabled regardless of the es0 bit value. [i 2 c slave address registers 0 to 2 (s0d0 to s0d2)] 0ff7 16 to 0ff9 16 the i 2 c slave address registers 0 to 2 (s0d0 to s0d2: addresses 0ff7 16 to 0ff9 16 ) consists of a 7-bit slave address and a read/ write bit. in the addressing mode, the slave address written in this register is compared with the address data to be received immedi- ately after the start condition is detected. ?bit 0: read/write bit (rwb) this is not used in the 7-bit addressing mode. in the 10-bit ad- dressing mode, the first address data to be received is compared with the contents (sad6 to sad0 + rwb) of the i 2 c slave address registers 0 to 2. the rwb bit is cleared to 0 automatically when the stop condi- tion is detected. ?bits 1 to 7: slave address (sad0Csad6) these bits store slave addresses. regardless of the 7-bit address- ing mode or the 10-bit addressing mode, the address data transmitted from the master is compared with these bits contents. fig. 63 structure of i 2 c slave address registers 0 to 2 s a d 6s a d 5s a d 4s a d 3s a d 2s a d 1s a d 0r w b s l a v e a d d r e s s i 2 c s l a v e a d d r e s s r e g i s t e r 0 ( s 0 d 0 : a d d r e s s 0 f f 7 1 6 ) i 2 c s l a v e a d d r e s s r e g i s t e r 1 ( s 0 d 1 : a d d r e s s 0 f f 8 1 6 ) i 2 c s l a v e a d d r e s s r e g i s t e r 2 ( s 0 d 2 : a d d r e s s 0 f f 9 1 6 ) r e a d / w r i t e b i t b 7b 0
69 3803/3804 group single-chip 8-bit cmos microcomputer mitsubishi microcomputers table 9 set values of i 2 c clock control register and scl frequency fig. 64 structure of i 2 c clock control register scl frequency (at f = 4 mhz, unit : khz) (note 1) setting value of ccr4Cccr0 standard clock mode setting disabled setting disabled setting disabled high-speed clock mode ccr4 0 0 0 0 0 0 0 1 1 1 ccr3 0 0 0 0 0 0 0 1 1 1 ccr2 0 0 0 0 1 1 1 1 1 1 ccr1 0 0 1 1 0 0 1 0 1 1 ccr0 0 1 0 1 0 1 0 1 0 1 setting disabled setting disabled setting disabled 34.5 33.3 32.3 100 83.3 333 250 400 (note 3) 166 C (note 2) C (note 2) [i 2 c clock control register (s2)] 0015 16 the i 2 c clock control register (s2: address 0015 16 ) is used to set ack control, scl mode and scl frequency. ?bits 0 to 4: scl frequency control bits (ccr0Cccr4) these bits control the scl frequency. refer to table 9. ?bit 5: scl mode specification bit (fast mode) this bit specifies the scl mode. when this bit is set to 0, the standard clock mode is selected. when the bit is set to 1, the high-speed clock mode is selected. when connecting the bus of the high-speed mode i 2 c bus stan- dard (maximum 400 kbits/s), use 8 mhz or more oscillation frequency f(x in ) in the high-speed mode (2 division clock). ?bit 6: ack bit (ack bit) this bit sets the sda status when an ack clock ] is generated. when this bit is set to 0, the ack return mode is selected and sda goes to l at the occurrence of an ack clock. when the bit is set to 1, the ack non-return mode is selected. the sda is held in the h status at the occurrence of an ack clock. however, when the slave address agree with the address data in the reception of address data at ack bit = 0, the sda is auto- matically made l (ack is returned). if there is a disagreement between the slave address and the address data, the sda is auto- matically made h (ack is not returned). ] ack clock: clock for acknowledgment ?bit 7: ack clock bit (ack) this bit specifies the mode of acknowledgment which is an ac- knowledgment response of data transfer. when this bit is set to 0, the no ack clock mode is selected. in this case, no ack clock occurs after data transmission. when the bit is set to 1, the ack clock mode is selected and the master generates an ack clock each completion of each 1-byte data transfer. the device for transmitting address data and control data releases the sda at the occurrence of an ack clock (makes sda h) and receives the ack bit generated by the data receiving device. note: do not write data into the i 2 c clock control register during transfer. if data is written during transfer, the i 2 c clock generator is reset, so that data cannot be transferred normally. 500/ccr value (note 3) 1000/ccr value (note 3) 17.2 16.6 16.1 notes 1: duty of scl output is 50 %. the duty becomes 35 to 45 % only when the high-speed clock mode is selected and ccr value = 5 (400 khz, at f = 4 mhz). h duration of the clock fluctuates from C4 to +2 machine cycles in the standard clock mode, and fluctu- ates from C2 to +2 machine cycles in the high-speed clock mode. in the case of negative fluctuation, the frequency does not in- crease because l duration is extended instead of h duration reduction. these are values when scl synchronization by the synchronous function is not performed. ccr value is the decimal notation value of the scl frequency control bits ccr4 to ccr0. 2: each value of scl frequency exceeds the limit at f = 4 mhz or more. when using these setting value, use f of 4 mhz or less. 3: the data formula of scl frequency is described below: f /(8 5 ccr value) standard clock mode f /(4 5 ccr value) high-speed clock mode (ccr value 1 5) f /(2 5 ccr value) high-speed clock mode (ccr value = 5) do not set 0 to 2 as ccr value regardless of f frequency. set 100 khz (max.) in the standard clock mode and 400 khz (max.) in the high-speed clock mode to the scl frequency by setting the scl frequency control bits ccr4 to ccr0. a c k a c k b i t f a s t m o d e c c r 4c c r 3 c c r 2c c r 1c c r 0 i 2 c c l o c k c o n t r o l r e g i s t e r ( s 2 : a d d r e s s 0 0 1 5 1 6 ) b 7b 0 s c l f r e q u e n c y c o n t r o l b i t s r e f e r t o t a b l e 9 . s c l m o d e s p e c i f i c a t i o n b i t 0 : s t a n d a r d c l o c k m o d e 1 : h i g h - s p e e d c l o c k m o d e a c k b i t 0 : a c k i s r e t u r n e d . 1 : a c k i s n o t r e t u r n e d . a c k c l o c k b i t 0 : n o a c k c l o c k 1 : a c k c l o c k
70 3803/3804 group single-chip 8-bit cmos microcomputer mitsubishi microcomputers fig. 65 structure of i 2 c control register [i 2 c control register (s1d)] 0014 16 the i 2 c control register (s1d: address 0014 16 ) controls data com- munication format. ?bits 0 to 2: bit counter (bc0Cbc2) these bits decide the number of bits for the next 1-byte data to be transmitted. the i 2 c interrupt request signal occurs immediately after the number of count specified with these bits (ack clock is added to the number of count when ack clock is selected by ack clock bit (bit 7 of s2, address 0015 16 ) have been transferred, and bc0 to bc2 are returned to 000 2 . also when a start condition is received, these bits become 000 2 and the address data is always transmitted and received in 8 bits. ?bit 3: i 2 c interface enable bit (es0) this bit enables to use the multi-master i 2 c-bus interface. when this bit is set to 0, the use disable status is provided, so that the sda and the scl become high-impedance. when the bit is set to 1, use of the interface is enabled. when es0 = 0, the following is performed. ? pin = 1, bb = 0 and al = 0 are set (which are bits of the i 2 c status register, s1, at address 0013 16 ). ? writing data to the i 2 c data shift register (s0: address 0011 16 ) is disabled. ?bit 4: data format selection bit (als) this bit decides whether or not to recognize slave addresses. when this bit is set to 0, the addressing format is selected, so that address data is recognized. when a match is found between a slave address and address data as a result of comparison or when a general call (refer to i 2 c status register, bit 1) is re- ceived, transfer processing can be performed. when this bit is set to 1, the free data format is selected, so that slave addresses are not recognized. ?bit 5: addressing format selection bit (10bit sad) this bit selects a slave address specification format. when this bit is set to 0, the 7-bit addressing format is selected. in this case, only the high-order 7 bits (slave address) of the i 2 c slave address registers 0 to 2 are compared with address data. when this bit is set to 1, the 10-bit addressing format is selected, and all the bits of the i 2 c slave address registers 0 to 2 are compared with ad- dress data. ?bit 7: i 2 c-bus interface pin input level selection bit this bit selects the input level of the scl and sda pins of the multi-master i 2 c-bus interface. b 7 t i s s 1 0 b i t s a d a l s e s 0b c 2b c 1b c 0 b 0 n o t u s e d ( r e t u r n 0 w h e n r e a d ) i 2 c c o n t r o l r e g i s t e r ( s 1 d : a d d r e s s 0 0 1 4 1 6 ) b i t c o u n t e r ( n u m b e r o f t r a n s m i t / r e c e i v e b i t s ) b 2b 1b 0 00 0: 8 00 1: 7 01 0: 6 01 1: 5 10 0: 4 10 1: 3 11 0: 2 11 1: 1 i 2 c - b u s i n t e r f a c e e n a b l e b i t 0 : d i s a b l e d 1 : e n a b l e d d a t a f o r m a t s e l e c t i o n b i t 0 : a d d r e s s i n g f o r m a t 1 : f r e e d a t a f o r m a t a d d r e s s i n g f o r m a t s e l e c t i o n b i t 0 : 7 - b i t a d d r e s s i n g f o r m a t 1 : 1 0 - b i t a d d r e s s i n g f o r m a t i 2 c - b u s i n t e r f a c e p i n i n p u t l e v e l s e l e c t i o n b i t 0 : c m o s i n p u t 1 : s m b u s i n p u t
71 3803/3804 group single-chip 8-bit cmos microcomputer mitsubishi microcomputers ?bit 4: scl pin low hold bit (pin) this bit generates an interrupt request signal. each time 1-byte data is transmitted, the pin bit changes from 1 to 0. at the same time, an interrupt request signal occurs to the cpu. the pin bit is set to 0 in synchronization with a falling of the last clock (in- cluding the ack clock) of an internal clock and an interrupt request signal occurs in synchronization with a falling of the pin bit. when the pin bit is 0, the scl is kept in the 0 state and clock generation is disabled. figure 67 shows an interrupt request signal generating timing chart. the pin bit is set to 1 in one of the following conditions: ? executing a write instruction to the i 2 c data shift register (s0: address 0011 16 ). (this is the only condition which the prohibition of the internal clock is released and data can be communicated except for the start condition detection.) ? when the es0 bit is 0 ? at reset ? when writing 1 to the pin bit by software the pin bit is set to 0 in one of the following conditions: ? immediately after completion of 1-byte data transmission (includ- ing when arbitration lost is detected) ? immediately after completion of 1-byte data reception ? in the slave reception mode, with als = 0 and immediately af- ter completion of slave address agreement or general call address reception ? in the slave reception mode, with als = 1 and immediately af- ter completion of address data reception ?bit 5: bus busy flag (bb) this bit indicates the status of use of the bus system. when this bit is set to 0, this bus system is not busy and a start condition can be generated. the bb flag is set/reset by the scl, sda pins input signal regardless of master/slave. this flag is set to 1 by detecting the start condition, and is set to 0 by detecting the stop condition. the condition of these detecting is set by the start/stop condition setting bits (ssc4Cssc0) of the i 2 c start/stop condition control register (s2d: address 0016 16 ). when the es0 bit of the i 2 c control register (bit 3 of s1d, address 0014 16 ) is 0 or reset, the bb flag is set to 0. for the writing function to the bb flag, refer to the sections start condition generating method and stop condition gen- erating method described later. [i 2 c status register (s1)] 0013 16 the i 2 c status register (s1: address 0013 16 ) controls the i 2 c-bus interface status. the low-order 4 bits are read-only bits and the high-order 4 bits can be read out and written to. set 0000 2 to the low-order 4 bits, because these bits become the reserved bits at writing. ?bit 0: last receive bit (lrb) this bit stores the last bit value of received data and can also be used for ack receive confirmation. if ack is returned when an ack clock occurs, the lrb bit is set to 0. if ack is not returned, this bit is set to 1. except in the ack mode, the last bit value of received data is input. the state of this bit is changed from 1 to 0 by executing a write instruction to the i 2 c data shift register (s0: address 0011 16 ). ?bit 1: general call detecting flag (ad0) when the als bit is 0, this bit is set to 1 when a general call ] whose address data is all 0 is received in the slave mode. by a general call of the master device, every slave device receives con- trol data after the general call. the ad0 bit is set to 0 by detecting the stop condition or start condition, or reset. ] general call: the master transmits the general call address 00 16 to all slaves. ?bit 2: slave address comparison flag (aas) this flag indicates a comparison result of address data when the als bit is 0. in the slave receive mode, when the 7-bit addressing format is selected, this bit is set to 1 in one of the following conditions: ? the address data immediately after occurrence of a start condition agrees with the slave address stored in the high-or- der 7 bits of the i 2 c slave address register. ? a general call is received. in the slave receive mode, when the 10-bit addressing format is selected, this bit is set to 1 with the following condition: ? when the address data is compared with the i 2 c slave ad- dress register (8 bits consisting of slave address and rbw bit), the first bytes agree. a this bit is set to 0 by executing a write instruction to the i 2 c data shift register (s0: address 0011 16 ) when es0 is set to 1 or reset. ?bit 3: arbitration lost ] detecting flag (al) in the master transmission mode, when the sda is made l by any other device, arbitration is judged to have been lost, so that this bit is set to 1. at the same time, the trx bit is set to 0, so that immediately after transmission of the byte whose arbitration was lost is completed, the mst bit is set to 0. the arbitration lost can be detected only in the master transmission mode. when ar- bitration is lost during slave address transmission, the trx bit is set to 0 and the reception mode is set. consequently, it becomes possible to detect the agreement of its own slave address and ad- dress data transmitted by another master device. ] arbitration lost : the status in which communication as a master is dis- abled.
72 3803/3804 group single-chip 8-bit cmos microcomputer mitsubishi microcomputers fig. 67 interrupt request signal generating timing fig. 66 structure of i 2 c status register ?bit 6: communication mode specification bit (transfer direc- tion specification bit: trx) this bit decides a direction of transfer for data communication. when this bit is 0, the reception mode is selected and the data of a transmitting device is received. when the bit is 1, the transmis- sion mode is selected and address data and control data are output onto the sda in synchronization with the clock generated on the scl. this bit is set/reset by software and hardware. about set/reset by hardware is described below. this bit is set to 1 by hardware when all the following conditions are satisfied: ? when als is 0 ? in the slave reception mode or the slave transmission mode ? when the r/w bit reception is 1 this bit is set to 0 in one of the following conditions: ? when arbitration lost is detected. ? when a stop condition is detected. ? when writing 1 to this bit by software is invalid by the start condition duplication preventing function (note) . ? with mst = 0 and when a start condition is detected. ? with mst = 0 and when ack non-return is detected. ? at reset ?bit 7: communication mode specification bit (master/slave specification bit: mst) this bit is used for master/slave specification for data communica- tion. when this bit is 0, the slave is specified, so that a start condition and a stop condition generated by the master are re- ceived, and data communication is performed in synchronization with the clock generated by the master. when this bit is 1, the master is specified and a start condition and a stop condition are generated. additionally, the clocks required for data communi- cation are generated on the scl. this bit is set to 0 in one of the following conditions. ? immediately after completion of 1-byte data transfer when arbi- tration lost is detected ? when a stop condition is detected. ? writing 1 to this bit by software is invalid by the start condi- tion duplication preventing function (note) . ? at reset note: start condition duplication preventing function the mst, trx, and bb bits is set to 1 at the same time after con- firming that the bb flag is 0 in the procedure of a start condition occurrence. however, when a start condition by another master device occurs and the bb flag is set to 1 immediately after the con- tents of the bb flag is confirmed, the start condition duplication preventing function makes the writing to the mst and trx bits in- valid. the duplication preventing function becomes valid from the rising of the bb flag to reception completion of slave address. b 7 m s t b 0 i 2 c s t a t u s r e g i s t e r ( s 1 : a d d r e s s 0 0 1 3 1 6 ) l a s t r e c e i v e b i t ( n o t e ) 0 :l a s t b i t = 0 1 :l a s t b i t = 1 g e n e r a l c a l l d e t e c t i n g f l a g ( n o t e ) 0 :n o g e n e r a l c a l l d e t e c t e d 1 :g e n e r a l c a l l d e t e c t e d s l a v e a d d r e s s c o m p a r i s o n f l a g ( n o t e ) 0 : a d d r e s s d i s a g r e e m e n t 1 : a d d r e s s a g r e e m e n t a r b i t r a t i o n l o s t d e t e c t i n g f l a g ( n o t e ) 0 :n o t d e t e c t e d 1 :d e t e c t e d s c l p i n l o w h o l d b i t 0 : s c l p i n l o w h o l d 1 : s c l p i n l o w r e l e a s e b u s b u s y f l a g 0 : b u s f r e e 1 : b u s b u s y c o m m u n i c a t i o n m o d e s p e c i f i c a t i o n b i t s 0 0 :s l a v e r e c e i v e m o d e 0 1 :s l a v e t r a n s m i t m o d e 1 0 :m a s t e r r e c e i v e m o d e 1 1 :m a s t e r t r a n s m i t m o d e t r xb bp i na la a sa d 0l r b n o t e : t h e s e b i t s a n d f l a g s c a n b e r e a d o u t , b u t c a n n o t b e w r i t t e n . w r i t e 0 t o t h e s e b i t s a t w r i t i n g . s c l p i n i 2 c i r q
73 3803/3804 group single-chip 8-bit cmos microcomputer mitsubishi microcomputers start condition generating method when writing 1 to the mst, trx, and bb bits of the i 2 c status register (s1: address 0013 16 ) at the same time after writing the slave address to the i 2 c data shift register (s0: address 0011 16 ) with the condition in which the es0 bit of the i 2 c control register (s1d: address 0014 16 ) and the bb flag are 0, a start condition occurs. after that, the bit counter becomes 000 2 and an scl for 1 byte is output. the start condition generating timing is differ- ent in the standard clock mode and the high-speed clock mode. refer to figure 68, the start condition generating timing dia- gram, and table 10, the start condition generating timing table. stop condition generating method when the es0 bit of the i 2 c control register (s1d: address 0014 16 ) is 1, write 1 to the mst and trx bits, and write 0 to the bb bit of the i 2 c status register (s1: address 0013 16 ) simulta- neously. then a stop condition occurs. the stop condition generating timing is different in the standard clock mode and the high-speed clock mode. refer to figure 69, the stop condition generating timing diagram, and table 11, the stop condition gen- erating timing table. fig. 68 start condition generating timing diagram fig. 69 stop condition generating timing diagram table 11 stop condition generating timing table item setup time hold time standard clock mode 5.0 m s (20 cycles) 4.5 m s (18 cycles) note: absolute time at f = 4 mhz. the value in parentheses denotes the number of f cycles. high-speed clock mode 3.0 m s (12 cycles) 2.5 m s (10 cycles) table 10 start condition generating timing table item setup time hold time standard clock mode 5.0 m s (20 cycles) 5.0 m s (20 cycles) note: absolute time at f = 4 mhz. the value in parentheses denotes the number of f cycles. high-speed clock mode 2.5 m s (10 cycles) 2.5 m s (10 cycles) i 2 c s t a t u s r e g i s t e r w r i t e s i g n a l h o l d t i m e s e t u p t i m e s c l s d a i 2 c s t a t u s r e g i s t e r w r i t e s i g n a l h o l d t i m e s e t u p t i m e s c l s d a
74 3803/3804 group single-chip 8-bit cmos microcomputer mitsubishi microcomputers fig. 70 start/stop condition detecting timing diagram start/stop condition detecting operation the start/stop condition detection operations are shown in figures 70, 71, and table 12. the start/stop condition is set by the start/stop condition set bit. the start/stop condition can be detected only when the input signal of the scl and sda pins satisfy three conditions: scl re- lease time, setup time, and hold time (see table 12). the bb flag is set to 1 by detecting the start condition and is reset to 0 by detecting the stop condition. the bb flag set/reset timing is different in the standard clock mode and the high-speed clock mode. refer to table 12, the bb flag set/ reset time. note: when a stop condition is detected in the slave mode (mst = 0), an interrupt request signal i 2 cirq occurs to the cpu. table 12 start condition/stop condition detecting conditions note: unit : cycle number of system clock f ssc value is the decimal notation value of the start/stop condi- tion set bits ssc4 to ssc0. do not set 0 or an odd number to ssc value. the value in parentheses is an example when the i 2 c start/ stop condition control register is set to 18 16 at f = 4 mhz. fig. 71 stop condition detecting timing diagram scl release time standard clock mode high-speed clock mode 4 cycles (1.0 m s) 2 cycles (1.0 m s) 2 cycles (0.5 m s) 3.5 cycles (0.875 m s) ssc value + 1 2 ssc value + 1 2 ssc value C1 2 setup time hold time bb flag set/ reset time ssc value + 1 cycle (6.25 m s) cycle < 4.0 m s (3.125 m s) cycle < 4.0 m s (3.125 m s) + 2 cycles (3.375 m s) h o l d t i m e s e t u p t i m e s c l s d a b b f l a g s c l r e l e a s e t i m e b b f l a g s e t t i m e h o l d t i m e s e t u p t i m e s c l s d a b b f l a g s c l r e l e a s e t i m e b b f l a g r e s e t t i m e
75 3803/3804 group single-chip 8-bit cmos microcomputer mitsubishi microcomputers [i 2 c start/stop condition control register (s2d)] 0016 16 the i 2 c start/stop condition control register (s2d: address 0016 16 ) controls start/stop condition detection. ?bits 0 to 4: start/stop condition set bit (ssc4Cssc0) scl release time, setup time, and hold time change the detection condition by value of the main clock divide ratio selection bit and the oscillation frequency f(x in ) because these time are measured by the internal system clock. accordingly, set the proper value to the start/stop condition set bits (ssc4 to ssc0) in considered of the system clock frequency. refer to table 12. do not set 00000 2 or an odd number to the start/stop condi- tion set bit (ssc4 to ssc0). refer to table 13, the recommended set value to start/stop condition set bits (ssc4Cssc0) for each oscillation frequency. ?bit 5: scl/sda interrupt pin polarity selection bit (sip) an interrupt can occur when detecting the falling or rising edge of the scl or sda pin. this bit selects the polarity of the scl or sda pin interrupt pin. ?bit 6: scl/sda interrupt pin selection bit (sis) this bit selects the pin of which interrupt becomes valid between the scl pin and the sda pin. note: when changing the setting of the scl/sda interrupt pin polarity se- lection bit, the scl/sda interrupt pin selection bit, or the i 2 c-bus interface enable bit es0, the scl/sda interrupt request bit may be set. when selecting the scl/sda interrupt source, disable the inter- rupt before the scl/sda interrupt pin polarity selection bit, the scl/ sda interrupt pin selection bit, or the i 2 c-bus interface enable bit es0 is set. reset the request bit to 0 after setting these bits, and enable the interrupt. ?bit 7: data receive mode at stop/low-speed mode bit (str) setting this bit to 1 enables to receive an address data even in the stop mode or the low-speed mode by making the built-in cr oscillator oscillate. the i 2 c interrupt request occurs and the pin bit changes to 0 from 1 when the address data agrees with the contents of i 2 c slave address register or a general call is received. the x in is not oscillating when receiving an address data. before performing communication after receiving an address data, start the x in oscil- lation using this interrupt and switch the main clock to high-speed or middle-speed mode. start/stop condition control register oscillation frequency f(x in ) (mhz) fig. 72 structure of i 2 c start/stop condition control register note: do not set an odd number to the start/stop condition set bit (ssc4 to ssc0) and 00000 2 . table 13 recommended set value to start/stop condition set bits (ssc4Cssc0) for each oscillation frequency main clock divide ratio system clock f (mhz) scl release time ( m s) setup time ( m s) hold time ( m s) 8 8 4 2 2 8 2 2 xxx11010 xxx11000 xxx00100 xxx01100 xxx01010 xxx00100 3.5 m s (14 cycles) 3.25 m s (13 cycles) 3.0 m s (3 cycles) 3.5 m s (7 cycles) 3.0 m s (6 cycles) 3.0 m s (3 cycles) 6.75 m s (27 cycles) 6.25 m s (25 cycles) 5.0 m s (5 cycles) 6.5 m s (13 cycles) 5.5 m s (11 cycles) 5.0 m s (5 cycles) 3.25 m s (13 cycles) 3.0 m s (12 cycles) 2.0 m s (2 cycles) 3.0 m s (6 cycles) 2.5 m s (5 cycles) 2.0 m s (2 cycles) 4 1 2 1 b 7b 0 i 2 c s t a r t / s t o p c o n d i t i o n c o n t r o l r e g i s t e r s t a r t / s t o p c o n d i t i o n s e t b i t s s c l / s d a i n t e r r u p t p i n p o l a r i t y s e l e c t i o n b i t 0 :f a l l i n g e d g e a c t i v e 1 :r i s i n g e d g e a c t i v e s c l / s d a i n t e r r u p t p i n s e l e c t i o n b i t 0 :s d a v a l i d 1 :s c l v a l i d d a t a r e c e i v e m o d e a t s t o p / l o w - s p e e d m o d e b i t 0 :m o d e i n v a l i d 1 :m o d e v a l i d s i ss i p s s c 4s s c 3s s c 2s s c 1s s c 0 ( s 2 d : a d d r e s s 0 0 1 6 1 6 ) s t r
76 3803/3804 group single-chip 8-bit cmos microcomputer mitsubishi microcomputers [i 2 c special mode status register (s3)] 0012 16 the i 2 c special mode status register (s3: address 0012 16 ) con- sists of the flags indicating i 2 c operating state in the i 2 c special mode, which is set by the i 2 c special mode control register (s3d: address 0017 16 ). the stop condition flag is valid in all operating modes. ?bit 0: slave address 0 comparison flag (aas0) bit 1: slave address 1 comparison flag (aas1) bit 2: slave address 2 comparison flag (aas2) these flags indicate a comparison result of address data. these flags are valid only when the slave address control bit (mslad) is 1. in the 7-bit addressing format of the slave reception mode, the re- spective slave address i (i = 0, 1, 2) comparison flags corresponding to the i 2 c slave address registers 0 to 2 are set to 1 when an address data immediately after an occurrence of a start condition agrees with the high-order 7-bit slave address stored in the i 2 c slave address registers 0 to 2 (addresses 0ff7 16 to 0ff9 16 ). in the 10-bit addressing format of the slave mode, the respective slave address i (i = 0, 1, 2) comparison flags corresponding to the i 2 c slave address registers are set to 1 when an address data is compared with the 8 bits consisting of the slave address stored in the i 2 c slave address registers 0 to 2 and the rwb bit, and the first byte agrees. these flags are initialized to 0 at reset, when the slave address control bit (mslad) is 0, or when writing data to the i 2 c data shift register (s0: address 0011 16 ). ?bit 4: time out flag (tiout) this flag is valid only when the data receive mode at stop/low- speed mode bit (str) and the i 2 c time out control bit (toen) are 1. this flag is set to 1 when the i 2 c bus communication does not end within about 26 ms at 8 mhz operating from an occur- rence of a start condition, owing to any reason. the scl/sda interrupt request simultaneously occurs. this flag is initialized to 0 in the following conditions: ? at reset ? when the i 2 c-bus interface enable bit (es0) is 0 ? when the i 2 c time out control bit (toen) is 0 ? when writing 1 to the time out flag clear bit (tofcl). ?bit 5: scl pin low hold 2 flag (pin2) when the ack interrupt control bit (ackicon) and the ack clock bit (ack) are 1, this flag is set to 0 in synchronization with the falling of the datas last scl clock, just before the ack clock. the scl pin is simultaneously held low, and the i 2 c interrupt request occurs. this flag is initialized to 1 at reset, when the ack interrupt con- trol bit (ackicon) is 0, or when writing 1 to the scl pin low hold 2 flag set bit (pin2in). the scl pin is held low when either the scl pin low hold bit (pin) or the scl pin low hold 2 flag (pin2) becomes 0. the low hold state of the scl pin is released when both the scl pin low hold bit (pin) and the scl pin low hold 2 flag (pin2) are 1. ?bit 7: stop condition flag (spcf) this flag is set to 1 when a stop condition occurs. this flag is initialized to 0 at reset, when the i 2 c-bus interface enable bit (es0) is 0, or when writing 1 to the stop condition flag clear bit (spfcl). fig. 73 structure of i 2 c special mode status register b 7b 0 i 2 c s p e c i a l m o d e s t a t u s r e g i s t e r ( s 3 : a d d r e s s 0 0 1 2 1 6 ) sl a v e a d d r e s s 0 c o m p a r i s o n f l a g 0 :a d d r e s s d i s a g r e e m e n t 1 :a d d r e s s a g r e e m e n t s t o p c o n d i t i o n f l a g 0 : n o d e t e c t i o n 1 : d e t e c t i o n a a s 0 a a s 1 a a s 2 t i o u t p i n 2 s p c f sl a v e a d d r e s s 1 c o m p a r i s o n f l a g 0 :a d d r e s s d i s a g r e e m e n t 1 :a d d r e s s a g r e e m e n t sl a v e a d d r e s s 2 c o m p a r i s o n f l a g 0 :a d d r e s s d i s a g r e e m e n t 1 :a d d r e s s a g r e e m e n t n o t u s e d ( r e t u r n 0 w h e n r e a d ) t i m e o u t f l a g 0 :n o t i m e o u t 1 :t i m e o u t o c c u r r e d n o t u s e d ( r e t u r n 0 w h e n r e a d ) s c l p i n l o w h o l d 2 f l a g 0 : s c l p i n l o w h o l d 1 : s c l p i n l o w r e l e a s e ( n o t e ) n o t e : i n o r d e r t h a t t h e l o w h o l d s t a t e o f t h e s c l p i n m a y r e l e a s e , i t i s n e c e s s a r y t h a t t h e s c l p i n l o w h o l d 2 f l a g a n d t h e s c l p i n l o w h o l d b i t ( p i n ) a r e 1 s i m u l t a n e o u s l y .
77 3803/3804 group single-chip 8-bit cmos microcomputer mitsubishi microcomputers [i 2 c special mode control register (s3d)] 0017 16 the i 2 c special mode control register (s3d: address 0017 16 ) con- trols special functions such as the time out function, occurrence timing of reception interrupt request and extending slave address comparison to 3 bytes. ?bit 0: i 2 c time out control bit (toen) in the condition that this bit and the data receive mode at stop/ low-speed mode bit (str) are 1, the time out flag (tiout) is set to 1 when the i 2 c bus communication does not end within about 26 ms at 8 mhz operating from an occurrence of a start condition, owing to any reason. the scl/sda interrupt request simulta- neously occurs. the time out function is disabled when the i 2 c time out control bit is 0. ?bit 1: ack interrupt control bit (ackicon) this bit controls the timing of i 2 c interrupt request occurrence at completion of data receiving due to master reception or slave re- ception. when this bit is 0, the scl pin low hold bit (pin) is set to 0 in synchronization with the falling of the last scl clock, including the ack clock. the scl pin is simultaneously held low, and the i 2 c interrupt request occurs. when this bit is 1 and the ack clock bit (ack) is 1, the scl pin low hold 2 flag (pin2) is set to 0 in synchronization with the fall- ing of the datas last scl clock, just before the ack clock. the scl pin is simultaneously held low, and the i 2 c interrupt request occurs again. the ack bit can be changed after the contents of data are confirmed by using this function. ?bit 2: i 2 c slave address control bit (mslad) this bit controls a slave address. when this bit is 0, only the i 2 c slave address register 0 (address 0ff7 16 ) becomes valid as a slave address and a read/write bit. when this bit is 1, all of the i 2 c slave address registers 0 to 2 (addresses 0ff7 16 to 0ff9 16 ) become valid as a slave address and a read/write bit. in this case, when an address data agrees with any one of the i 2 c slave address registers 0 to 2, the slave address comparison flag (aas) is set to 1 and the i 2 c slave ad- dress comparison flag corresponding to the agreed i 2 c slave address registers 0 to 2 is also set to 1. ?bit 4: time out flag clear bit (tofcl) writing 1 to this bit initializes the time out flag to 0. when writing 0, nothing is generated. ?bit 5: scl pin low hold 2 flag set bit (pin2in) writing 1 to this bit initializes the scl pin low hold 2 flag (pin2) to 1. when writing 0, nothing is generated. ?bit 6: scl pin low hold set bit (pin2hd) when the scl pin low hold bit (pin) becomes 0, the scl pin is held low. however, the scl pin low hold bit (pin) cannot be set to 0 by software. the scl pin low hold set bit (pin2hd) is used to , hold the scl pin in the low state by software. when writing 1 to this bit, the scl pin low hold 2 flag (pin2) becomes 0, and the scl pin is held low. when writing 0, nothing occurs. ?bit 7: stop condition flag clear bit (spfcl) writing 1 to this bit initializes the stop condition flag (spcf) to 0. when writing 0, nothing is generated. fig. 74 structure of i 2 c special mode control register b 7b 0 i 2 c s p e c i a l m o d e c o n t r o l r e g i s t e r ( s 3 d : a d d r e s s 0 0 1 7 1 6 ) i 2 c t i m e o u t c o n t r o l b i t 0 :d i s a b l e d 1 :e n a b l e d s t o p c o n d i t i o n f l a g c l e a r b i t w r i t i n g 1 t o t h i s b i t i n i t i a l i z e s t h e s t o p c o n d i t i o n f l a g t o 0 . t o e n a c k i c o n ms l a d t o f c l p i n 2 i n s p f c l a c k i n t e r r u p t c o n t r o l b i t 0 :a t c o m m u n i c a t i o n c o m p l e t i o n 1 :a t f a l l i n g o f a c k c l o c k a n d c o m m u n i c a t i o n c o m p l e t i o n s l a v e a d d r e s s c o n t r o l b i t 0 :o n e - b y t e s l a v e a d d r e s s c o m p a r e m o d e 1 :t h r e e - b y t e s l a v e a d d r e s s c o m p a r e m o d e n o t u s e d ( r e t u r n 0 w h e n r e a d ) t i m e o u t f l a g c l e a r b i t w r i t i n g 1 t o t h i s b i t i n i t i a l i z e s t h e t i m e o u t f l a g t o 0 . s c l p i n l o w h o l d 2 f l a g s e t b i t ( n o t e ) w r i t i n g 1 t o t h i s b i t i n i t i a l i z e s t h e s c l p i n l o w h o l d 2 f l a g t o 1 . p i n 2 - h d s c l p i n l o w h o l d s e t b i t ( n o t e ) w h e n wr i t i n g 1 t o t h i s b i t , t h e s c l p i n l o w h o l d 2 f l a g b e c o m e s 0 a n d t h e s c l p i n i s h e l d l o w . n o t e : d o n o t w r i t e 1 t o t h e s e b i t s s i m u l t a n e o u s l y .
78 3803/3804 group single-chip 8-bit cmos microcomputer mitsubishi microcomputers fig. 75 address data communication format address data communication there are two address data communication formats, namely, 7-bit addressing format and 10-bit addressing format. the respective address communication formats are described below. 7-bit addressing format to adapt the 7-bit addressing format, set the 10bit sad bit of the i 2 c control register (s1d: address 0014 16 ) to 0. the first 7- bit address data transmitted from the master is compared with the high-order 7-bit slave address stored in the i 2 c slave ad- dress register. at the time of this comparison, address comparison of the rwb bit of the i 2 c slave address register is not performed. for the data transmission format when the 7-bit addressing format is selected, refer to figure 75, (1) and (2). 10-bit addressing format to adapt the 10-bit addressing format, set the 10bit sad bit of the i 2 c control register (s1d: address 0014 16 ) to 1. an ad- dress comparison is performed between the first-byte address data transmitted from the master and the 8-bit slave address stored in the i 2 c slave address register. at the time of this com- parison, an address comparison between the rwb bit of the i 2 c slave address register and the r/w bit which is the last bit of the address data transmitted from the master is made. in the 10-bit addressing mode, the rwb bit which is the last bit of the address data not only specifies the direction of communication for control data, but also is processed as an address data bit. when the first-byte address data agree with the slave address, the aas bit of the i 2 c status register (s1: address 0013 16 ) is set to 1. after the second-byte address data is stored into the i 2 c data shift register (s0: address 0011 16 ), perform an ad- dress comparison between the second-byte data and the slave address by software. when the address data of the 2 bytes agree with the slave address, set the rwb bit of the i 2 c slave address register to 1 by software. this processing can make the 7-bit slave address and r/w data agree, which are re- ceived after a restart condition is detected, with the value of the i 2 c slave address register. for the data transmission for- mat when the 10-bit addressing format is selected, refer to figure 75, (3) and (4). ss l a v e a d d r e s sr / w a d a t a a / a p a d a t a 7 b i t s 0 ? t o 8 b i t s1 t o 8 b i t s ( 1 ) a m a s t e r - t r a n s m i t t e r t r a n s n m i t s d a t a t o a s l a v e - r e c e i v e r ss l a v e a d d r e s sr / w a d a t a a p a d a t a 7 b i t s 1 ? t o 8 b i t s1 t o 8 b i t s ( 2 ) a m a s t e r - r e c e i v e r r e c e i v e s d a t a f r o m a s l a v e - t r a n s m i t t e r 7 b i t s 0 ? b i t s ( 3 ) a m a s t e r - t r a n s m i t t e r t r a n s m i t s d a t a t o a s l a v e - r e c e i v e r w i t h a 1 0 - b i t a d d r e s s 1 t o 8 b i t s1 t o 8 b i t s sr / w a s l a v e a d d r e s s 1 s t 7 b i t s s l a v e a d d r e s s 2 n d b y t e s a ad a t a d a t a p a / a 7 b i t s 0 ? b i t s ( 4 ) a m a s t e r - r e c e i v e r r e c e i v e s d a t a f r o m a s l a v e - t r a n s m i t t e r w i t h a 1 0 - b i t a d d r e s s s : s t a r t c o n d i t i o n a : a c k b i t s r : r e s t a r t c o n d i t i o n p : s t o p c o n d i t i o n r / w : r e a d / w r i t e b i t 7 b i t s 1 ? t o 8 b i t s1 t o 8 b i t s sr / w a s l a v e a d d r e s s 1 s t 7 b i t s s l a v e a d d r e s s 2 n d b y t e s a s r s l a v e a d d r e s s 1 s t 7 b i t s r / w a d a t a d a t a p a : m a s t e r t o s l a v e : s l a v e t o m a s t e r a
79 3803/3804 group single-chip 8-bit cmos microcomputer mitsubishi microcomputers example of master transmission an example of master transmission in the standard clock mode, at the scl frequency of 100 khz and in the ack return mode is shown below. set a slave address in the high-order 7 bits of the i 2 c slave ad- dress register and 0 into the rwb bit. set the ack return mode and scl = 100 khz by setting 85 16 in the i 2 c clock control register (s2: address 0015 16 ). a set 00 16 in the i 2 c status register (s1: address 0013 16 ) so that transmission/reception mode can become initializing condi- tion. ? set a communication enable status by setting 08 16 in the i 2 c control register (s1d: address 0014 16 ). ? confirm the bus free condition by the bb flag of the i 2 c status register (s1: address 0013 16 ). ? set the address data of the destination of transmission in the high-order 7 bits of the i 2 c data shift register (s0: address 0011 16 ) and set 0 in the least significant bit. ? set f0 16 in the i 2 c status register (s1: address 0013 16 ) to generate a start condition. at this time, an scl for 1 byte and an ack clock automatically occur. ? set transmit data in the i 2 c data shift register (s0: address 0011 16 ). at this time, an scl and an ack clock automatically occur. when transmitting control data of more than 1 byte, repeat step ? . set d0 16 in the i 2 c status register (s1: address 0013 16 ) to generate a stop condition if ack is not returned from slave re- ception side or transmission ends. example of slave reception an example of slave reception in the high-speed clock mode, at the scl frequency of 400 khz, in the ack non-return mode and using the addressing format is shown below. set a slave address in the high-order 7 bits of the i 2 c slave ad- dress register and 0 in the rwb bit. set the no ack clock mode and scl = 400 khz by setting 25 16 in the i 2 c clock control register (s2: address 0015 16 ). a set 00 16 in the i 2 c status register (s1: address 0013 16 ) so that transmission/reception mode can become initializing condi- tion. ? set a communication enable status by setting 08 16 in the i 2 c control register (s1d: address 0014 16 ). ? when a start condition is received, an address comparison is performed. ? ?when all transmitted addresses are 0 (general call): ad0 of the i 2 c status register (s1: address 0013 16 ) is set to 1 and an interrupt request signal occurs. ? when the transmitted addresses agree with the address set in : aas of the i 2 c status register (s1: address 0013 16 ) is set to 1 and an interrupt request signal occurs. ? in the cases other than the above ad0 and ass of the i 2 c sta- tus register (s1: address 0013 16 ) are set to 0 and no interrupt request signal occurs. ? set dummy data in the i 2 c data shift register (s0: address 0011 16 ). ? when receiving control data of more than 1 byte, repeat step ? . when a stop condition is detected, the communication ends.
80 3803/3804 group single-chip 8-bit cmos microcomputer mitsubishi microcomputers (2) start condition generating procedure using multi-master 1. procedure example (the necessary conditions of the generat- ing procedure are described as the following 2 to 5. : : lda (taking out of slave address value) sei (interrupt disabled) bbs 5, s1, busbusy (bb flag confirming and branch process) busfree: sta s0 (writing of slave address value) ldm #$f0, s1 (trigger of start condition generating) cli (interrupt enabled) : : busbusy: cli (interrupt enabled) : : 2. use branch on bit set of bbs 5, $0014, C for the bb flag confirming and branch process. 3. use sta $12, stx $12 or sty $12 of the zero page ad- dressing instruction for writing the slave address value to the i 2 c data shift register. 4. execute the branch instruction of above 2 and the store instruc- tion of above 3 continuously shown the above procedure example. 5. disable interrupts during the following three process steps: ? bb flag confirming ? writing of slave address value ? trigger of start condition generating when the condition of the bb flag is bus busy, enable interrupts immediately. (3) restart condition generating procedure 1. procedure example (the necessary conditions of the generat- ing procedure are described as the following 2 to 4.) execute the following procedure when the pin bit is 0. : : ldm #$00, s1 (select slave receive mode) lda (t aking out of slave address value) sei (interrupt disabled) sta s0 (writing of slave address value) ldm #$f0, s1 ( trigger of restart condition generating ) cli (interrupt enabled) : : 2. select the slave receive mode when the pin bit is 0. do not write 1 to the pin bit. neither 0 nor 1 is specified for the writing to the bb bit. the trx bit becomes 0 and the sda pin is released. 3. the scl pin is released by writing the slave address value to the i 2 c data shift register. 4. disable interrupts during the following two process steps: ? writing of slave address value ? trigger of restart condition generating (4) writing to i 2 c status register do not execute an instruction to set the pin bit to 1 from 0 and an instruction to set the mst and trx bits to 0 from 1 simulta- neously. it is because it may enter the state that the scl pin is released and the sda pin is released after about one machine cycle. do not execute an instruction to set the mst and trx bits to 0 from 1 simultaneously when the pin bit is 1. it is because it may become the same as above. (5) process of after stop condition generating do not write data in the i 2 c data shift register s0 and the i 2 c sta- tus register s1 until the bus busy flag bb becomes 0 after generating the stop condition in the master mode. it is because the stop condition waveform might not be normally generated. reading to the above registers does not have the problem. n precautions when using multi-master i 2 c- bus interface (1) read-modify-write instruction the precautions when the read-modify-write instruction such as seb, clb etc. is executed for each register of the multi-master i 2 c-bus interface are described below. ?i 2 c data shift register (s0: address 0011 16 ) when executing the read-modify-write instruction for this regis- ter during transfer, data may become a value not intended. ?i 2 c slave address registers 0 to 2 (s0d0 to s0d2: addresses 0ff7 16 to0ff9 16 ) when the read-modify-write instruction is executed for this regis- ter at detecting the stop condition, data may become a value not intended. it is because h/w changes the read/write bit (rwb) at the above timing. ?i 2 c status register (s1: address 0013 16 ) do not execute the read-modify-write instruction for this register because all bits of this register are changed by h/w. ?i 2 c control register (s1d: address 0014 16 ) when the read-modify-write instruction is executed for this regis- ter at detecting the start condition or at completing the byte transfer, data may become a value not intended. because h/w changes the bit counter (bc0-bc2) at the above timing. ?i 2 c clock control register (s2: address 0015 16 ) the read-modify-write instruction can be executed for this regis- ter. ?i 2 c start/stop condition control register (s2d: address 0016 16 ) the read-modify-write instruction can be executed for this regis- ter.
81 3803/3804 group single-chip 8-bit cmos microcomputer mitsubishi microcomputers reset circuit to reset the microcomputer, reset pin should be held at an "l" level for 2 m s or more. then the reset pin is returned to an "h" level (the power source voltage should be between 2.7 v and 5.5 v, and the oscillation should be stable), reset is released. after the reset is completed, the program starts from the address contained in address fffd 16 (high-order byte) and address fffc 16 (low-or- der byte). make sure that the reset input voltage is less than 0.54 v for v cc of 2.7 v. fig. 77 reset sequence fig. 76 reset circuit example reset internal reset data f address sync x in : 10.5 to 18.5 clock cycles x in ? ? ? ? ? fffc fffd ad h , l ? ? ? ? ? ad l ad h 1: the frequency relation of f(x in ) and f( f ) is f(x in )=8 f( f ). 2: th e ques ti o n m a rk s ( ? ) in d i ca t e a n u n de fin ed s t a t e th a t de p e n ds o n th e pr e vi ous s t a t e . reset address from the vector table. notes (note) 0.2v cc 0v 0v poweron v cc reset v cc reset power source voltage detection circuit power source voltage reset input voltage note : reset release voltage ; vcc=2.7 v
82 3803/3804 group single-chip 8-bit cmos microcomputer mitsubishi microcomputers fig. 78 internal status at reset (3803 group) note : x : not fixed since the initial values for other than above mentioned registers and ram contents are indefinite at reset, they must be set. (1) (2) (3) (4) (5) (6) (7) (8) (9) (10) (11) (12) (13) (14) (15) (16) (17) (18) (19) (20) (21) (22) (23) (24) (25) (26) (27) (28) (29) (30) (31) (32) (33) (34) (35) (36) (37) (38) (39) (40) (41) (42) (43) (44) (45) (46) (47) (48) (49) (50) (51) (52) (53) (54) (55) (56) (57) (58) (59) (60) (61) (62) (63) (64) (65) (66) (67) register contents 0028 16 0029 16 002a 16 002b 16 002c 16 002d 16 002f 16 0030 16 0031 16 0032 16 0033 16 0034 16 0035 16 0036 16 0037 16 0038 16 0039 16 003a 16 003b 16 003c 16 003d 16 003e 16 003f 16 0ff0 16 0ff1 16 0ff2 16 0ff3 16 0ff4 16 0ff5 16 0ff6 16 0ffe 16 0fff 16 (ps) (pc h ) (pc l ) address ff 16 ff 16 00 16 00 16 00 16 00 16 00 16 00 16 00 16 00 16 00 16 00 16 00 16 00 16 00 16 00 16 00 16 00 16 00 16 00 16 00 16 00 16 address register contents 00 16 00 16 00 16 00 16 00 16 00 16 00 16 00 16 00 16 00 16 00 16 00 16 00 16 00 16 00 16 00 16 00 16 ff 16 01 16 ff 16 00 16 ff 16 ff 16 ff 16 ff 16 1110 0 0 xxxxxxxx 001 11111 xxxxxxxx 1 fffd 16 contents fffc 16 contents xx xx xx x port p0 (p0) port p0 direction register (p0d) port p1 (p1) port p1 direction register (p1d) port p2 (p2) port p2 direction register (p2d) port p3 (p3) port p3 direction register (p3d) port p4 (p4) port p4 direction register (p4d) port p5 (p5) port p5 direction register (p5d) port p6 (p6) port p6 direction register (p6d) timer 12, x count source selection register (t12xcss) timer y, z count source selection register (tyzcss) misrg transmit/receive buffer register 1 (tb1/rb1) serial i/o1 status register (sio1sts) serial i/o1 control register (sio1con) uart1 control register (uart1con) baud rate generator 1 (brg1) serial i/o2 control register (sio2con) watchdog timer control register (wdtcon) serial i/o2 register (sio2) prescaler 12 (pre12) timer 1 (t1) timer 2 (t2) timer xy mode register (tm) prescaler x (prex) timer x (tx) prescaler y (prey) timer y (ty) 0011 0011 0011 0011 xxxxxxxx 10000000 00 xxxxxxxx 0000 16 0001 16 0002 16 0003 16 0004 16 0005 16 0006 16 0007 16 0008 16 0009 16 000a 16 000b 16 000c 16 000d 16 000e 16 000f 16 0010 16 0018 16 0019 16 001a 16 001b 16 001c 16 001d 16 001e 16 001f 16 0020 16 0021 16 0022 16 0023 16 0024 16 0025 16 0026 16 0027 16 xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx 10 00 00 00 11100000 00001000 xx 000000 01001000 timer z (low-order) (tzl) timer z (high-order) (tzh) timer z mode register (tzm) pwm control register (pwmcon) pwm prescaler (prepwm) pwm register (pwm) baud rate generator 3 (brg3) transmit/receive buffer register 3 (tb3/rb3) serial i/o3 status register (sio3sts) serial i/o3 control register (sio3con) uart3 control register (sio3con) ad/da control register (adcon) a-d conversion register 1 (ad1) d-a1 conversion register (da1) d- a2 conversion register (da2) a- d conversion register 2 (ad2) interrupt source selection register (intsel) interrupt edge selection register (intedge) cpu mode register (cpum) interrupt request register 1 (ireq1) interrupt request register 2 (ireq2) interrupt control register 1 (icon1) interrupt control register 2 (icon2) port p0 pull-up control register (pull0) port p1 pull-up control register (pull1) port p2 pull-up control register (pull2) port p3 pull-up control register (pull3) port p4 pull-up control register (pull4) port p5 pull-up control register (pull5) port p6 pull-up control register (pull6) flash memory control register (fcon) flash command register (fcmd) processor status register program counter
83 3803/3804 group single-chip 8-bit cmos microcomputer mitsubishi microcomputers fig. 79 internal status at reset (3804 group) n o t e : x : n o t f i x e d s i n c e t h e i n i t i a l v a l u e s f o r o t h e r t h a n a b o v e m e n t i o n e d r e g i s t e r s a n d r a m c o n t e n t s a r e i n d e f i n i t e a t r e s e t , t h e y m u s t b e s e t . ( 1 ) ( 2 ) ( 3 ) ( 4 ) ( 5 ) ( 6 ) ( 7 ) ( 8 ) ( 9 ) ( 1 0 ) ( 1 1 ) ( 1 2 ) ( 1 3 ) ( 1 4 ) ( 1 5 ) ( 1 6 ) ( 1 7 ) ( 1 8 ) ( 1 9 ) ( 2 0 ) ( 2 1 ) ( 2 2 ) ( 2 3 ) ( 2 4 ) ( 2 5 ) ( 2 6 ) ( 2 7 ) ( 2 8 ) ( 2 9 ) ( 3 0 ) ( 3 1 ) ( 3 2 ) ( 3 3 ) ( 3 4 ) ( 3 5 ) ( 3 6 ) ( 3 7 ) ( 3 8 ) ( 3 9 ) ( 4 0 ) ( 4 1 ) ( 4 2 ) ( 4 3 ) ( 4 4 ) ( 4 5 ) ( 4 6 ) ( 4 7 ) ( 4 8 ) ( 4 9 ) ( 5 0 ) ( 5 1 ) ( 5 2 ) ( 5 3 ) ( 5 4 ) ( 5 5 ) ( 5 6 ) ( 5 7 ) ( 5 8 ) ( 5 9 ) ( 6 0 ) ( 6 1 ) ( 6 2 ) ( 6 3 ) ( 6 4 ) ( 6 5 ) ( 6 6 ) ( 6 7 ) ( 6 8 ) ( 6 9 ) ( 7 0 ) ( 7 1 ) ( 7 2 ) ( 7 3 ) ( 7 4 ) ( 7 5 ) ( 7 6 ) ( 7 7 ) r e g i s t e r c o n t e n t s a d d r e s s f f 1 6 f f 1 6 0 0 1 6 0 0 1 6 0 0 1 6 0 0 1 6 0 0 1 6 0 0 1 6 0 0 1 6 0 0 1 6 0 0 1 6 0 0 1 6 0 0 1 6 0 0 1 6 0 0 1 6 0 0 1 6 0 0 1 6 0 0 1 6 0 0 1 6 0 0 1 6 0 0 1 6 0 0 1 6 0 0 1 6 0 0 1 6 0 0 1 6 a d d r e s sr e g i s t e r c o n t e n t s 0 0 1 6 0 0 1 6 0 0 1 6 0 0 1 6 0 0 1 6 0 0 1 6 0 0 1 6 0 0 1 6 0 0 1 6 0 0 1 6 0 0 1 6 0 0 1 6 0 0 1 6 0 0 1 6 0 0 1 6 0 0 1 6 0 0 1 6 0 0 1 6 0 0 1 6 0 0 1 6 f f 1 6 0 1 1 6 f f 1 6 0 0 1 6 f f 1 6 f f 1 6 f f 1 6 f f 1 6 1110 0 0 xxxxxxxx 00111111 xxxxxxxx 1 f f f d 1 6 c o n t e n t s f f f c 1 6 c o n t e n t s xx xx xx x p o r t p 0 ( p 0 ) p o r t p 0 d i r e c t i o n r e g i s t e r ( p 0 d ) p o r t p 1 ( p 1 ) p o r t p 1 d i r e c t i o n r e g i s t e r ( p 1 d ) p o r t p 2 ( p 2 ) p o r t p 2 d i r e c t i o n r e g i s t e r ( p 2 d ) p o r t p 3 ( p 3 ) p o r t p 3 d i r e c t i o n r e g i s t e r ( p 3 d ) p o r t p 4 ( p 4 ) p o r t p 4 d i r e c t i o n r e g i s t e r ( p 4 d ) p o r t p 5 ( p 5 ) p o r t p 5 d i r e c t i o n r e g i s t e r ( p 5 d ) p o r t p 6 ( p 6 ) p o r t p 6 d i r e c t i o n r e g i s t e r ( p 6 d ) t i m e r 1 2 , x c o u n t s o u r c e s e l e c t i o n r e g i s t e r ( t 1 2 x c s s ) t i m e r y , z c o u n t s o u r c e s e l e c t i o n r e g i s t e r ( t y z c s s ) m i s r g i 2 c d a t a s h i f t r e g i s t e r ( s 0 ) i 2 c s p e c i a l m o d e s t a t u s r e g i s t e r ( s 3 ) i 2 c s t a t u s r e g i s t e r ( s 1 ) i 2 c c o n t r o l r e g i s t e r ( s 1 d ) i 2 c c l o c k c o n t r o l r e g i s t e r ( s 2 ) i 2 c s t a r t / s t o p c o n d i t i o n c o n t o l r e g i s t e r ( s 2 d ) i 2 c s p e c i a l m o d e c o n t r o l r e g i s t e r ( s 3 d ) t r a n s m i t / r e c e i v e b u f f e r r e g i s t e r 1 ( t b 1 / r b 1 ) s e r i a l i / o 1 s t a t u s r e g i s t e r ( s i o 1 s t s ) s e r i a l i / o 1 c o n t r o l r e g i s t e r ( s i o 1 c o n ) u a r t 1 c o n t r o l r e g i s t e r ( u a r t 1 c o n ) b a u d r a t e g e n e r a t o r 1 ( b r g 1 ) s e r i a l i / o 2 c o n t r o l r e g i s t e r ( s i o 2 c o n ) w a t c h d o g t i m e r c o n t r o l r e g i s t e r ( w d t c o n ) s e r i a l i / o 2 r e g i s t e r ( s i o 2 ) p r e s c a l e r 1 2 ( p r e 1 2 ) t i m e r 1 ( t 1 ) t i m e r 2 ( t 2 ) t i m e r x y m o d e r e g i s t e r ( t m ) p r e s c a l e r x ( p r e x ) t i m e r x ( t x ) p r e s c a l e r y ( p r e y ) t i m e r y ( t y ) 00110011 00110011 xxxxxxxx 10000000 00 xxxxxxxx 0 0 0 0 1 6 0 0 0 1 1 6 0 0 0 2 1 6 0 0 0 3 1 6 0 0 0 4 1 6 0 0 0 5 1 6 0 0 0 6 1 6 0 0 0 7 1 6 0 0 0 8 1 6 0 0 0 9 1 6 0 0 0 a 1 6 0 0 0 b 1 6 0 0 0 c 1 6 0 0 0 d 1 6 0 0 0 e 1 6 0 0 0 f 1 6 0 0 1 0 1 6 0 0 1 1 1 6 0 0 1 2 1 6 0 0 1 3 1 6 0 0 1 4 1 6 0 0 1 5 1 6 0 0 1 6 1 6 0 0 1 7 1 6 0 0 1 8 1 6 0 0 1 9 1 6 0 0 1 a 1 6 0 0 1 b 1 6 0 0 1 c 1 6 0 0 1 d 1 6 0 0 1 e 1 6 0 0 1 f 1 6 0 0 2 0 1 6 0 0 2 1 1 6 0 0 2 2 1 6 0 0 2 3 1 6 0 0 2 4 1 6 0 0 2 5 1 6 0 0 2 6 1 6 0 0 2 7 1 6 xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx 10000000 11100000 00001000 xx 000000 01001000 t i m e r z ( l o w - o r d e r ) ( t z l ) t i m e r z ( h i g h - o r d e r ) ( t z h ) t i m e r z m o d e r e g i s t e r ( t z m ) p w m c o n t r o l r e g i s t e r ( p w m c o n ) p w m p r e s c a l e r ( p r e p w m) p w m r e g i s t e r ( p w m ) b a u d r a t e g e n e r a t o r 3 ( b r g 3 ) t r a n s m i t / r e c e i v e b u f f e r r e g i s t e r 3 ( t b 3 / r b 3 ) s e r i a l i / o 3 s t a t u s r e g i s t e r ( s i o 3 s t s ) s e r i a l i / o 3 c o n t r o l r e g i s t e r ( s i o 3 c o n ) u a r t 3 c o n t r o l r e g i s t e r ( s i o 3 c o n ) a d / d a c o n t r o l r e g i s t e r ( a d c o n ) a - d c o n v e r s i o n r e g i s t e r 1 ( a d 1 ) d - a 1 c o n v e r s i o n r e g i s t e r ( d a 1 ) d - a 2 c o n v e r s i o n r e g i s t e r ( d a 2 ) a - d c o n v e r s i o n r e g i s t e r 2 ( a d 2 ) i n t e r r u p t s o u r c e s e l e c t i o n r e g i s t e r ( i n t s e l ) i n t e r r u p t e d g e s e l e c t i o n r e g i s t e r ( i n t e d g e ) c p u m o d e r e g i s t e r ( c p u m ) i n t e r r u p t r e q u e s t r e g i s t e r 1 ( i r e q 1 ) i n t e r r u p t r e q u e s t r e g i s t e r 2 ( i r e q 2 ) i n t e r r u p t c o n t r o l r e g i s t e r 1 ( i c o n 1 ) i n t e r r u p t c o n t r o l r e g i s t e r 2 ( i c o n 2 ) p o r t p 0 p u l l - u p c o n t r o l r e g i s t e r ( p u l l 0 ) p o r t p 1 p u l l - u p c o n t r o l r e g i s t e r ( p u l l 1 ) p o r t p 2 p u l l - u p c o n t r o l r e g i s t e r ( p u l l 2 ) p o r t p 3 p u l l - u p c o n t r o l r e g i s t e r ( p u l l 3 ) p o r t p 4 p u l l - u p c o n t r o l r e g i s t e r ( p u l l 4 ) p o r t p 5 p u l l - u p c o n t r o l r e g i s t e r ( p u l l 5 ) p o r t p 6 p u l l - u p c o n t r o l r e g i s t e r ( p u l l 6 ) i 2 c s l a v e a d d r e s s r e g i s t e r 0 ( s 0 d 0 ) i 2 c s l a v e a d d r e s s r e g i s t e r 1 ( s 0 d 1 ) i 2 c s l a v e a d d r e s s r e g i s t e r 2 ( s 0 d 3 ) f l a s h m e m o r y c o n t r o l r e g i s t e r ( f c o n ) f l a s h c o m m a n d r e g i s t e r ( f c m d ) p r o c e s s o r s t a t u s r e g i s t e r p r o g r a m c o u n t e r xxxxxxxx 00100000 0001000x 00011010 0 0 2 8 1 6 0 0 2 9 1 6 0 0 2 a 1 6 0 0 2 b 1 6 0 0 2 c 1 6 0 0 2 d 1 6 0 0 2 f 1 6 0 0 3 0 1 6 0 0 3 1 1 6 0 0 3 2 1 6 0 0 3 3 1 6 0 0 3 4 1 6 0 0 3 5 1 6 0 0 3 6 1 6 0 0 3 7 1 6 0 0 3 8 1 6 0 0 3 9 1 6 0 0 3 a 1 6 0 0 3 b 1 6 0 0 3 c 1 6 0 0 3 d 1 6 0 0 3 e 1 6 0 0 3 f 1 6 0 f f 0 1 6 0 f f 1 1 6 0 f f 2 1 6 0 f f 3 1 6 0 f f 4 1 6 0 f f 5 1 6 0 f f 6 1 6 0 f f 7 1 6 0 f f 8 1 6 0 f f 9 1 6 0 f f e 1 6 0 f f f 1 6 ( p s ) ( p c h ) ( p c l ) 3
84 3803/3804 group single-chip 8-bit cmos microcomputer mitsubishi microcomputers clock generating circuit the m38039ffsp/fp has two built-in oscillation circuits. an oscil- lation circuit can be formed by connecting a resonator between x in and x out (x cin and x cout ). use the circuit constants in ac- cordance with the resonator manufacturers recommended values. no external resistor is needed between x in and x out since a feed-back resistor exists on-chip. however, an external feed-back resistor is needed between x cin and x cout . immediately after power on, only the x in oscillation circuit starts oscillating, and x cin and x cout pins function as i/o ports. frequency control (1) middle-speed mode the internal clock f is the frequency of x in divided by 8. after re- set, this mode is selected. (2) high-speed mode the internal clock f is half the frequency of x in . (3) low-speed mode the internal clock f is half the frequency of x cin . n note if you switch the mode between middle/high-speed and low- speed, stabilize both x in and x cin oscillations. the sufficient time is required for the sub clock to stabilize, especially immediately af- ter power on and at returning from stop mode. when switching the mode between middle/high-speed and low-speed, set the fre- quency on condition that f(x in ) > 3f(x cin ). (4) low power dissipation mode the low power consumption operation can be realized by stopping the main clock x in in low-speed mode. to stop the main clock, set bit 5 of the cpu mode register to 1. when the main clock x in is restarted (by setting the main clock stop bit to 0), set sufficient time for oscillation to stabilize. oscillation control (1) stop mode if the stp instruction is executed, the internal clock f stops at an h level, and x in and x cin oscillators stop. when the oscillation stabilizing time set after stp instruction released bit is 0, the prescaler 12 is set to ff 16 and timer 1 is set to 01 16 . when the oscillation stabilizing time set after stp instruction released bit is 1, set the sufficient time for oscillation of used oscillator to stabi- lize since nothing is set to the prescaler 12 and timer 1. after stp instruction is released, the input of the prescaler 12 is connected to count source which had set at executing the stp in- struction, and the output of the prescaler 12 is connected to timer 1. set the timer 1 interrupt enable bit to disabled (0) before ex- ecuting the stp instruction. oscillator restarts when an external interrupt is received, but the internal clock f is not supplied to the cpu (remains at h) until timer 1 underflows. the internal clock f is supplied for the first time, when timer 1 underflows. therefore make sure not to set the timer 1 interrupt request bit to 1 before the stp instruction stops the oscillator. when the oscillator is re- started by reset, apply l level to the reset pin until the oscillation is stable since a wait time will not be generated. (2) wait mode if the wit instruction is executed, the internal clock f stops at an h level, but the oscillator does not stop. the internal clock f re- starts when an interrupt is received or reset. since the oscillator does not stop, normal operation can be started immediately after the clock is restarted.
85 3803/3804 group single-chip 8-bit cmos microcomputer mitsubishi microcomputers fig. 80 ceramic resonator circuit fig. 81 external clock input circuit v cc v ss x cin x cout x in x out open open external oscillation circuit external oscillation circuit v cc v ss x cin x cout x in x out c in c out c cin c cout rf rd
86 3803/3804 group single-chip 8-bit cmos microcomputer mitsubishi microcomputers wit instruction stp instruction timing f (internal clock) s r q stp instruction s r q main clock stop bit s r q 1/2 1/4 x in x out x cout x cin interrupt request reset interrupt disable flag l port x c switch bit ? ? low-speed mode high-speed or middle-speed mode middle-speed mode high-speed or low-speed mode main clock division ratio selection bits (note 1) notes 1: either high-speed, middle-speed or low-speed mode is selected by bits 7 and 6 of the cpu mode register. when low-speed mode is selected, set port xc switch bit (b4) to ?? 2: f(x in )/16 is supplied as the count source to the prescaler 12 at reset. the count source which is set before stp instruction is executed is supplied as the count source to the prescaler 12 at executing the stp instruction. main clock division ratio selection bits (note 1) ff 16 01 16 prescaler 12 timer 1 reset or stp instruction (note 2) divider fig. 82 system clock generating circuit block diagram (single-chip mode)
87 3803/3804 group single-chip 8-bit cmos microcomputer mitsubishi microcomputers fig. 83 state transitions of system clock c m 4 : p o r t x c s w i t c h b i t 0 : i / o p o r t f u n c t i o n ( s t o p o s c i l l a t i n g ) 1 : x c i n - x c o u t o s c i l l a t i n g f u n c t i o n c m 5 : m a i n c l o c k ( x i n - x o u t ) s t o p b i t 0 : o p e r a t i n g 1 : s t o p p e d c m 7 , c m 6 : m a i n c l o c k d i v i s i o n r a t i o s e l e c t i o n b i t b 7 b 6 0 0 : f = f ( x i n ) / 2 ( h i g h - s p e e d m o d e ) 0 1 : f = f ( x i n ) / 8 ( m i d d l e - s p e e d m o d e ) 1 0 : f = f ( x c i n ) / 2 ( l o w - s p e e d m o d e ) 1 1 : n o t a v a i l a b l e r e s e t c m 4 1 ? ? 0 c m 4 0 ? ? 1 c m 6 1 ? ? 0 c m 4 1 ? ? 0 c m 6 1 ? ? 0 c m 7 1 ? ? 0 c m 4 1 ? ? 0 c m 5 1 ? ? 0 c m 6 1 ? ? 0 c m 6 1 ? ? 0 c p u m o d e r e g i s t e r b 7b 4 c m 7 0 ? ? 1 c m 6 1 ? ? 0 ( c p u m : a d d r e s s 0 0 3 b 1 6 ) c m 7 = 0 c m 6 = 1 c m 5 = 0 ( 8 m h z o s c i l l a t i n g ) c m 4 = 0 ( 3 2 k h z s t o p p e d ) m i d d l e - s p e e d m o d e ( f ( f ) = 1 m h z ) c m 7 = 0 c m 6 = 1 c m 5 = 0 ( 8 m h z o s c i l l a t i n g ) c m 4 = 1 ( 3 2 k h z o s c i l l a t i n g ) m i d d l e - s p e e d m o d e ( f ( f ) = 1 m h z ) c m 7 = 0 c m 6 = 0 c m 5 = 0 ( 8 m h z o s c i l l a t i n g ) c m 4 = 0 ( 3 2 k h z s t o p p e d ) h i g h - s p e e d m o d e ( f ( f ) = 4 m h z ) c m 7 = 1 c m 6 = 0 c m 5 = 0 ( 8 m h z o s c i l l a t i n g ) c m 4 = 1 ( 3 2 k h z o s c i l l a t i n g ) l o w - s p e e d m o d e ( f ( f ) = 1 6 k h z ) c m 7 = 1 c m 6 = 0 c m 5 = 1 ( 8 m h z s t o p p e d ) c m 4 = 1 ( 3 2 k h z o s c i l l a t i n g ) l o w - s p e e d m o d e ( f ( f ) = 1 6 k h z ) c m 7 = 0 c m 6 = 0 c m 5 = 0 ( 8 m h z o s c i l l a t i n g ) c m 4 = 1 ( 3 2 k h z o s c i l l a t i n g ) a h i g h - s p e e d m o d e ( f ( f ) = 4 m h z ) 1 : s w i t c h t h e m o d e b y t h e a l l o w s s h o w n b e t w e e n t h e m o d e b l o c k s . ( d o n o t s w i t c h b e t w e e n t h e m o d e s d i r e c t l y w i t h o u t a n a l l o w . ) 2 : t h e a l l m o d e s c a n b e s w i t c h e d t o t h e s t o p m o d e o r t h e w a i t m o d e a n d r e t u r n t o t h e s o u r c e m o d e w h e n t h e s t o p m o d e o r t h e w a i t m o d e i s e n d e d . 3 : t i m e r o p e r a t e s i n t h e w a i t m o d e . 4 : w h e n t h e s t o p m o d e i s e n d e d , a d e l a y o f a p p r o x i m a t e l y 1 m s o c c u r s b y c o n n e c t i n g p r e s c a l e r 1 2 a n d t i m e r 1 i n m i d d l e / h i g h - s p e e d m o d e . 5 : w h e n t h e s t o p m o d e i s e n d e d , a d e l a y o f a p p r o x i m a t e l y 0 . 2 5 s o c c u r s b y t i m e r 1 a n d t i m e r 2 i n l o w - s p e e d m o d e . 6 : w a i t u n t i l o s c i l l a t i o n s t a b i l i z e s a f t e r o s c i l l a t i n g t h e m a i n c l o c k x i n b e f o r e t h e s w i t c h i n g f r o m t h e l o w - s p e e d m o d e t o m i d d l e / h i g h - s p e e d m o d e . 7 : t h e e x a m p l e a s s u m e s t h a t 8 m h z i s b e i n g a p p l i e d t o t h e x i n p i n a n d 3 2 k h z t o t h e x c i n p i n . f i n d i c a t e s t h e i n t e r n a l c l o c k .
88 3803/3804 group single-chip 8-bit cmos microcomputer mitsubishi microcomputers flash memory mode the 3803/3804 group has the flash memory mode in addition to the normal operation mode (microcomputer mode). the user can use this mode to perform read, program, and erase operations for the internal flash memory. the 3803/3804 group has three modes the user can choose: the parallel input/output and serial input/output mode, where the flash memory is handled by using the external programmer, and the cpu reprogramming mode, where the flash memory is handled by the central processing unit (cpu). the following explains these modes. (1) flash memory mode 1 (parallel i/o mode) the parallel i/o mode can be selected by connecting wires as shown in figures 84 and supplying power to the v cc and v pp pins. in this mode, the m38039ffsp/fp operates as an equiva- lent of mitsubishis cmos flash memory m5m28f101. however, because the m38039ffsp/fps internal memory has a capacity of 60 kbytes, programming is available for addresses 01000 16 to 0ffff 16 , and make sure that the data in addresses 00000 16 to 00fff 16 and addresses 10000 16 to 1ffff 16 are ff 16 . note also that the m38039ffsp/fp does not contain a facility to read out a device identification code by applying a high voltage to address input (a9). be careful not to erratically set program condi- tions when using a general-purpose prom programmer. table 14 shows the pin assignments when operating in the paral- lel input/output mode. table 14 pin assignments of m38039ffsp/fp when operating in the parallel input/output mode v cc v pp v ss address input data i/o __ ce ___ oe ___ we m38039ffsp/fp v cc cnv ss v ss ports p0, p1, p3 1 port p2 p3 6 p3 7 p3 3 m5m28f101 v cc v pp v ss a 0 Ca 16 d 0 Cd 7 __ ce __ oe ___ we functional outline (parallel input/output mode) in the parallel input/output mode, the 3803/3804 group allow the user to choose an operation mode between the read-only mode and the read/write mode (software command control mode) de- pending on the voltage applied to the v pp pin. when v pp = v pp l, the read-only mode is selected, and the user can choose one of three states (e.g., read, output disable, or standby) depending on ___ ___ ___ inputs to the ce, oe, and we pins. when v pp = v pp h, the read/ write mode is selected, and the user can choose one of four states (e.g., read, output disable, standby, or write) depending on inputs __ __ ___ to the ce, oe, and we pins. table 15 shows assignment states of control input and each state. l read __ the microcomputer enters the read state by driving the ce, and __ ___ oe pins low and the we pin high; and the contents of memory corresponding to the address to be input to address input pins (a 0 Ca 16 ) are output to the data input/output pins (d 0 Cd 7 ). l output disable the microcomputer enters the output disable state by driving the __ ___ __ ce pin low and the we and oe pins high; and the data input/out- put pins enter the floating state. l standby __ the microcomputer enters the standby state by driving the ce pin high. the 3803/3804 group is placed in a power-down state con- suming only a minimam supply current. at this time, the data input/ output pins enter the floating state. l write the microcomputer enters the write state by driving the v pp pin ___ __ high (v pp = v pp h) and then the we pin low when the ce pin is __ low and the oe pin is high. in this state, software commands can be input from the data input/output pins, and the user can choose program or erase operation depending on the contents of this soft- ware command. pin mode read output disable standby read output disable standby write read-only read/write __ ce v il v il v ih v il v il v ih v il v il v ih v il v ih v ih table 15 assignment states of control input and each state __ oe ___ we v ih v ih v ih v ih v il v pp l v pp l v pp l v pp h v pp h v pp h v pp h v pp output floating floating output floating floating input data i/o note: can be v il or v ih . state
89 3803/3804 group single-chip 8-bit cmos microcomputer mitsubishi microcomputers supply 5 v 10 % to v cc and 0 v to v ss . connect to 5 v 10 % in read-only mode, connect to 11.7 v to 12.6 v in read/write mode. connect to v ss . connect a ceramic resonator between x in and x out . connect to v ss . connect to v ss . port p0 functions as 8-bit address input (a 0 Ca 7 ). port p1 functions as 8-bit address input (a 8 Ca 15 ). function as 8-bit datas i/o pins (d 0 Cd 7 ). __ __ ___ p3 7 , p3 6 and p3 3 function as the oe, ce and we input pins respectively. p3 1 functions as the a 16 input pin. connect p3 0 and p3 2 to v ss . input h or l to p3 4 , p3 5 , or keep them open. connect p4 4 , p4 6 to v ss . input h or l to p4 0 - p4 3, p4 5 , p4 7 , or keep them open. input h or l, or keep them open. input h or l, or keep them open. power supply v pp input reset input clock input clock output analog supply input reference voltage input address input (a 0 Ca 7 ) address input (a 8 Ca 15 ) data i/o (d 0 Cd 7 ) control signal input input port p4 input port p5 input port p6 table 16 pin description (flash memory parallel i/o mode) pin name input input input output input input input i/o input input input input input /output functions v cc , v ss cnv ss _____ reset x in x out av ss v ref p0 0 Cp0 7 p1 0 Cp1 7 p2 0 Cp2 7 p3 0 Cp3 7 p4 0 Cp4 7 p5 0 Cp5 7 p6 0 Cp6 7
90 3803/3804 group single-chip 8-bit cmos microcomputer mitsubishi microcomputers fig. 84 pin connection of m38039fffp/hp when operating in parallel input/output mode outline 64p6n-a/64p6q-a 3 2 3 1 3 0 2 9 2 8 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 4 9 5 0 5 1 5 2 5 3 5 4 5 5 5 6 5 7 5 8 5 9 6 0 6 1 6 2 6 3 2 7 6 4 4 8 4 7 4 6 4 5 4 3 4 2 4 1 4 0 3 9 3 8 3 7 3 6 3 5 3 4 3 3 4 4 1 2 3 4 5 6 7 8 9 1 0 1 1 1 2 1 3 1 4 1 5 1 6 m 3 8 0 3 9 f f f p / h p p 0 0 / a n 8 p 0 1 / a n 9 p 0 2 / a n 1 0 p 0 3 / a n 1 1 p 0 4 / a n 1 2 p 0 5 / a n 1 3 p 0 6 / a n 1 4 p 0 7 / a n 1 5 p 1 0 p 1 1 p 1 2 p 1 3 p 1 6 p 1 4 p 1 5 p 1 7 p 2 7 ( l e d 7 ) p 2 0 ( l e d 0 ) p 2 1 ( l e d 1 ) p 2 2 ( l e d 2 ) p 2 3 ( l e d 3 ) p 2 4 ( l e d 4 ) p 2 5 ( l e d 5 ) p 2 6 ( l e d 6 ) v s s x o u t x i n p 4 2 / i n t 1 r e s e t c n v s s p 4 0 / i n t 4 / x c o u t p 4 1 / i n t 0 / x c i n p 3 5 p 3 4 p 3 1 / d a 2 p 3 0 / d a 1 v c c v r e f a v s s p 6 7 / a n 7 p 6 6 / a n 6 p 6 5 / a n 5 p 6 4 / a n 4 p 6 3 / a n 3 p 3 7 p 3 6 p 3 3 p 3 2 p 6 1 / a n 1 p 6 0 / a n 0 p 5 7 / i n t 3 p 5 6 / p w m p 5 5 / c n t r 1 p 5 4 / c n t r 0 p 5 2 / s c l k 2 p 5 1 / s o u t 2 p 5 0 / s i n 2 p 4 6 / s c l k 1 p 4 5 / t x d 1 p 4 4 / r x d 1 p 4 3 / i n t 2 p 6 2 / a n 2 p 4 7 / s r d y 1 p 5 3 / s r d y 2 a 0 a 1 a 2 a 3 a 4 a 5 a 6 a 7 a 8 a 9 a 1 0 a 1 1 a 1 2 a 1 3 a 1 4 a 1 5 d 0 d 1 d 2 d 3 d 4 d 5 d 6 d 7 v s s ] o e c e w e a 1 6 v c c :connect to the ceramic oscillation circuit. indicates the flash memory pin. * v p p
91 3803/3804 group single-chip 8-bit cmos microcomputer mitsubishi microcomputers fig. 85 pin connection of m38039ffsp when operating in parallel input/output mode outline 64p4b 6 4 6 3 6 2 6 1 6 0 5 9 5 8 5 7 5 6 5 5 5 4 5 3 5 2 5 1 5 0 4 9 4 8 4 7 4 6 4 5 4 2 4 4 4 3 4 1 4 0 3 9 3 8 3 7 3 6 3 5 3 4 3 3 1 2 3 4 5 6 7 8 9 1 0 1 1 1 2 1 3 1 4 1 5 1 6 1 7 1 8 1 9 2 0 2 2 2 3 2 4 2 5 2 6 2 7 2 8 2 9 3 0 3 1 3 2 2 1 m 3 8 0 3 9 f f s p v c c v r e f a v s s p 6 7 / a n 7 p 6 6 / a n 6 p 6 4 / a n 4 p 6 3 / a n 3 p 6 2 / a n 2 p 6 1 / a n 1 p 6 0 / a n 0 p 5 7 / i n t 3 p 5 6 / p w m p 5 5 / c n t r 1 p 5 4 / c n t r 0 p 5 2 / s c l k 2 p 5 1 / s o u t 2 p 5 0 / s i n 2 p 4 6 / s c l k 1 p 4 5 / t x d 1 p 4 4 / r x d 1 p 4 3 / i n t 2 p 4 2 / i n t 1 c n v s s p 4 0 / i n t 4 / x c o u t x i n x o u t v s s r e s e t p 3 0 / d a 1 p 3 1 / d a 2 p 3 4 p 3 5 p 0 0 / a n 8 p 2 0 / ( l e d 0 ) p 5 3 / s r d y 2 p 6 5 / a n 5 p 4 1 / i n t 0 / x c i n p 0 1 / a n 9 p 0 2 / a n 1 0 p 0 3 / a n 1 1 p 0 4 / a n 1 2 p 0 5 / a n 1 3 p 0 6 / a n 1 4 p 0 7 / a n 1 5 p 1 0 p 1 1 p 1 2 p 1 3 p 1 4 p 1 5 p 1 6 p 1 7 p 2 1 / ( l e d 1 ) p 2 2 / ( l e d 2 ) p 2 3 / ( l e d 3 ) p 2 4 / ( l e d 4 ) p 2 5 / ( l e d 5 ) p 2 6 / ( l e d 6 ) p 2 7 / ( l e d 7 ) p 3 2 p 3 3 p 3 6 p 3 7 p 4 7 / s r d y 1 d 0 d 1 d 2 d 3 d 4 d 5 d 6 d 7 a 8 a 9 a 1 0 a 1 1 a 1 2 a 1 3 a 1 4 a 1 5 a 0 a 1 a 2 a 3 a 4 a 5 a 6 a 7 o e c e w e a 1 6 v s s v c c :connect to the ceramic oscillation circuit. indicates the flash memory pin. * ] v p p
92 3803/3804 group single-chip 8-bit cmos microcomputer mitsubishi microcomputers read-only mode the microcomputer enters the read-only mode by applying v pp l to the v pp pin. in this mode, the user can input the address of a memory location to be read and the control signals at the timing shown in figure 86, and the m38039ffsp/fp will output the con- tents of the users specified address from data i/o pin to the external. in this mode, the user cannot perform any operation other than read. fig. 86 read timing read/write mode the microcomputer enters the read/write mode by applying v pp h to the v pp pin. in this mode, the user must first input a software command to choose the operation (e. g., read, program, or erase) to be performed on the flash memory (this is called the first cycle), and then input the information necessary for execution of the com- mand (e.g, address and data) and control signals (this is called the second cycle). when this is done, the 3803/3804 group ex- ecutes the specified operation. table 17 shows the software commands and the input/output in- formation in the first and the second cycles. the input address is ___ latched internally at the falling edge of the we input; software commands and other input data are latched internally at the rising ___ edge of the we input. the following explains each software command. refer to figures 87 to 89 for details about the signal input/output timings. table 17 software command (parallel input/output mode) symbol read program program verify erase erase verify reset device identification address input verify address first cycle data input 00 16 40 16 c0 16 20 16 a0 16 ff 16 90 16 address input read address program address adi second cycle data i/o read data (output) program data (input) verify data (output) 20 16 (input) verify data (output) ff 16 (input) ddi (output) note: adi = device identification address : manufacturers code 00000 16 , device code 00001 16 ddi = device identification data : manufacturers code 1c 16 , device code d0 16 x can be v il or v ih . address valid address t rc t a(ce) t wrr t df t a(oe) t dh t olz floating floating t clz t a(ad) v ih v il v ih v il v ih v il v ih v il v oh v ol ce oe we data dout
93 3803/3804 group single-chip 8-bit cmos microcomputer mitsubishi microcomputers l read command the microcomputer enters the read mode by inputting command code 00 16 in the first cycle. the command code is latched into ___ the internal command latch at the rising edge of the we input. when the address of a memory location to be read is input in the second cycle, with control signals input at the timing shown in fig- ure 87, the 3803/3804 group outputs the contents of the specified address from the data i/o pins to the external. the read mode is retained until any other command is latched into the command latch. consequently, once the 3803/3804 group en- ters the read mode, the user can read out the successive memory contents simply by changing the input address and executing the second cycle only. any command other than the read command must be input beginning from its command code over again each time the user execute it. the contents of the command latch immedi- ately after power-on is 00 16 . fig. 87 timings during reading address valid address t wc t ch t cs t rc t a(ce) t df t wrr t wp t rrw t a(oe) t dh t dh t vsc t clz t olz t ds t a(ad) v ih v il v ih v il v ih v il v ih v il v ih v il v pp h v pp l ce oe we data v pp dout 00 16
94 3803/3804 group single-chip 8-bit cmos microcomputer mitsubishi microcomputers l program command the microcomputer enters the program mode by inputting com- mand code 40 16 in the first cycle. the command code is latched ___ into the internal command latch at the rising edge of the we input. when the address which indicates a program location and data is input in the second cycle, the 3803/3804 group internally latches ___ the address at the falling edge of the we input and the data at the ___ rising edge of the we input. the 3803/3804 group starts program- ___ ming at the rising edge of the we input in the second cycle and finishes programming within 10 m s as measured by its internal timer. programming is performed in units of bytes. note: a programming operation is not completed by executing the program command once. always be sure to execute a pro- gram verify command after executing the program command. when the failure is found in this verification, the user must re- peatedly execute the program command until the pass. refer to figure 90 for the programming flowchart. l program verify command the microcomputer enters the program verify mode by inputting command code c0 16 in the first cycle. this command is used to verify the programmed data after executing the program com- mand. the command code is latched into the internal command ___ latch at the rising edge of the we input. when control signals are input in the second cycle at the timing shown in figure 88, the 3803/3804 group outputs the programmed addresss contents to the external. since the address is internally latched when the pro- gram command is executed, there is no need to input it in the second cycle. fig. 88 input/output timings during programming (verify data is output at the same timing as for read.) address program program verify program address t wc t cs t rrw t wp t wph t wp t dp t ds 40 16 d in c0 16 dout t ds t dh t dh verify data output t dh t vsc t ds t wp t wrr t cs t cs t ch t ch t ch t as t ah v ih v il v ih v il v ih v il v ih v il v ih v il v pp h v pp l ce oe we data v pp
95 3803/3804 group single-chip 8-bit cmos microcomputer mitsubishi microcomputers l erase command the erase command is executed by inputting command code 20 16 in the first cycle and command code 20 16 again in the second cycle. the command code is latched into the internal command ___ latch at the rising edges of the we input in the first cycle and in the second cycle, respectively. the erase operation is initiated at ___ the rising edge of the we input in the second cycle, and the memory contents are collectively erased within 9.5 ms as mea- sured by the internal timer. note that data 00 16 must be written to all memory locations before executing the erase command. note: an erase operation is not completed by executing the erase command once. always be sure to execute an erase verify command after executing the erase command. when the fail- ure is found in this verification, the user must repeatedly ex- ecute the erase command until the pass. refer to figure 90 for the erase flowchart. fig. 89 input/output timings during erasing (verify data is output at the same timing as for read.) l erase verify command the user must verify the contents of all addresses after complet- ing the erase command. the microcomputer enters the erase verify mode by inputting the verify address and command code a0 16 in the first cycle. the address is internally latched at the fall- ___ ing edge of the we input, and the command code is internally ___ latched at the rising edge of the we input. when control signals are input in the second cycle at the timing shown in figure 89, the 3803/3804 group outputs the contents of the specified address to the external. note: if any memory location where the contents have not been erased is found in the erase verify operation, execute the op- eration of erase ? erase verify over again. in this case, however, the user does not need to write data 00 16 to memory locations before erasing. address erase erase verify verify address t wc t cs t rrw t wp t wph t wp t de t ds 20 16 20 16 a0 16 dout t ds t dh t dh verify data output t dh t vsc t ds t wp t wrr t cs t cs t ch t ch t ch t as t ah v ih v il v ih v il v ih v il v ih v il v ih v il v pp h v pp l ce oe we data v pp
96 3803/3804 group single-chip 8-bit cmos microcomputer mitsubishi microcomputers l reset command the reset command provides a means of stopping execution of the erase or program command safely. if the user inputs command code ff 16 in the second cycle after inputting the erase or program command in the first cycle and again input command code ff 16 in the third cycle, the erase or program command is disabled (i.e., reset), and the 3803/3804 group is placed in the read mode. if the reset command is executed, the contents of the memory does not change. l device identification code command by inputting command code 90 16 in the first cycle, the user can read out the device identification code. the command code is latched into the internal command latch at the rising edge of the ___ we input. at this time, the user can read out manufactures code 1c 16 (i.e., mitsubishi) by inputting 00000 16 to the address input pins in the second cycle; the user can read out device code d0 16 (i. e., 1m-bit flash memory) by inputting 00001 16 . these command and data codes are input/output at the same tim- ing as for read.
97 3803/3804 group single-chip 8-bit cmos microcomputer mitsubishi microcomputers fig. 90 programming/erasing algorithm flow chart start v cc = 5 v, v pp = v pp h adrs = first location x = 0 write program command write program data duration = 10 m s x = x + 1 write program-verify command 40 16 d in c0 16 00 16 duration = 6 m s x = 25 ? last adrs ? no inc adrs write read command v pp = v pp l device passed device failed verify byte ? verify byte ? fail fail program erase yes yes no pass pass start v cc = 5 v, v pp = v pp h adrs = first location x = 0 write erase command program all bytes = 00 16 all bytes = 00 16 ? write erase command duration = 9.5 ms x = x + 1 write erase-verify command 20 16 20 16 a0 16 00 16 duration = 6 m s x = 1000 ? last adrs ? no inc adrs write read command v pp = v pp l device passed device failed verify byte ? verify byte ? fail fail yes yes no pass pass yes no
98 3803/3804 group single-chip 8-bit cmos microcomputer mitsubishi microcomputers table 18 dc electrical characteristics (t a = 25 c, v cc = 5 v 10 %, unless otherwise noted) symbol max. 1 100 15 15 15 10 100 100 30 30 0.8 v cc 0.45 v cc + 1.0 12.6 __ v cc = 5.5 v, ce = v ih v cc = 5.5 v, __ ce = v cc 0.2 v __ v cc = 5.5 v, ce = v il , t rc = 150 ns, i out = 0 ma v pp = v pp h v pp = v pp h 0 v pp v cc v cc 99 3803/3804 group single-chip 8-bit cmos microcomputer mitsubishi microcomputers (2) flash memory mode 2 (serial i/o mode) the flash memory version of the 3803/3804 group has a function to serially input/output the software commands, addresses, and data required for operation on the internal flash memory (e. g., read, program, and erase) using only a few pins. this is called the serial i/o (input/output) mode. this mode can be selected by driv- ing the sda (serial data input/output), sclk (serial clock input ), __ and oe pins high after connecting wires as shown in figures 91 and powering on the v cc pin and then applying v pp h to the v pp pin. in the serial i/o mode, the user can use six types of software com- mands: read, program, program verify, erase, erase verify and error check. serial input/output is accomplished synchronously with the clock, beginning from the lsb (lsb first). fig. 91 pin connection of m38039fffp/hp when operating in serial i/o mode outline 64p6n-a/64p6q-a 3 2 3 1 3 0 2 9 2 8 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 4 9 5 0 5 1 5 2 5 3 5 4 5 5 5 6 5 7 5 8 5 9 6 0 6 1 6 2 6 3 2 7 6 4 4 8 4 7 4 6 4 5 4 3 4 2 4 1 4 0 3 9 3 8 3 7 3 6 3 5 3 4 3 3 4 4 1 2 3 4 5 6 7 8 9 1 0 1 1 1 2 1 3 1 4 1 5 1 6 m 3 8 0 3 9 f f f p / h p p 0 0 / a n 8 p 0 1 / a n 9 p 0 2 / a n 1 0 p 0 3 / a n 1 1 p 0 4 / a n 1 2 p 0 5 / a n 1 3 p 0 6 / a n 1 4 p 0 7 / a n 1 5 p 1 0 p 1 1 p 1 2 p 1 3 p 1 6 p 1 4 p 1 5 p 1 7 p 2 7 ( l e d 7 ) p 2 0 ( l e d 0 ) p 2 1 ( l e d 1 ) p 2 2 ( l e d 2 ) p 2 3 ( l e d 3 ) p 2 4 ( l e d 4 ) p 2 5 ( l e d 5 ) p 2 6 ( l e d 6 ) v s s x o u t x i n p 4 2 / i n t 1 r e s e t c n v s s p 4 0 / i n t 4 / x c o u t p 4 1 / i n t 0 / x c i n p 3 5 p 3 4 p 3 1 / d a 2 p 3 0 / d a 1 v c c v r e f a v s s p 6 7 / a n 7 p 6 6 / a n 6 p 6 5 / a n 5 p 6 4 / a n 4 p 6 3 / a n 3 p 3 7 p 3 6 p 3 3 p 3 2 p 6 1 / a n 1 p 6 0 / a n 0 p 5 7 / i n t 3 p 5 6 / p w m p 5 5 / c n t r 1 p 5 4 / c n t r 0 p 5 2 / s c l k 2 p 5 1 / s o u t 2 p 5 0 / s i n 2 p 4 6 / s c l k 1 p 4 5 / t x d 1 p 4 4 / r x d 1 p 4 3 / i n t 2 p 6 2 / a n 2 p 4 7 / s r d y 1 p 5 3 / s r d y 2 v p p v s s ] o e v c c s d a s c l k b u s y : c o n n e c t t o t h e c e r a m i c o s c i l l a t i o n c i r c u i t . i n d i c a t e s t h e f l a s h m e m o r y p i n . ]
100 3803/3804 group single-chip 8-bit cmos microcomputer mitsubishi microcomputers fig. 92 pin connection of m38039ffsp when operating in serial i/o mode outline 64p4b 6 4 6 3 6 2 6 1 6 0 5 9 5 8 5 7 5 6 5 5 5 4 5 3 5 2 5 1 5 0 4 9 4 8 4 7 4 6 4 5 4 2 4 4 4 3 4 1 4 0 3 9 3 8 3 7 3 6 3 5 3 4 3 3 1 2 3 4 5 6 7 8 9 1 0 1 1 1 2 1 3 1 4 1 5 1 6 1 7 1 8 1 9 2 0 2 2 2 3 2 4 2 5 2 6 2 7 2 8 2 9 3 0 3 1 3 2 2 1 m 3 8 0 3 9 f f s p v c c v r e f a v s s p 6 7 / a n 7 p 6 6 / a n 6 p 6 4 / a n 4 p 6 3 / a n 3 p 6 2 / a n 2 p 6 1 / a n 1 p 6 0 / a n 0 p 5 7 / i n t 3 p 5 6 / p w m p 5 5 / c n t r 1 p 5 4 / c n t r 0 p 5 2 / s c l k 2 p 5 1 / s o u t 2 p 5 0 / s i n 2 p 4 6 / s c l k 1 p 4 5 / t x d 1 p 4 4 / r x d 1 p 4 3 / i n t 2 p 4 2 / i n t 1 c n v s s p 4 0 / i n t 4 / x c o u t x i n x o u t v s s r e s e t p 3 0 / d a 1 p 3 1 / d a 2 p 3 4 p 3 5 p 0 0 / a n 8 p 2 0 / ( l e d 0 ) p 5 3 / s r d y 2 p 6 5 / a n 5 p 4 1 / i n t 0 / x c i n p 0 1 / a n 9 p 0 2 / a n 1 0 p 0 3 / a n 1 1 p 0 4 / a n 1 2 p 0 5 / a n 1 3 p 0 6 / a n 1 4 p 0 7 / a n 1 5 p 1 0 p 1 1 p 1 2 p 1 3 p 1 4 p 1 5 p 1 6 p 1 7 p 2 1 / ( l e d 1 ) p 2 2 / ( l e d 2 ) p 2 3 / ( l e d 3 ) p 2 4 / ( l e d 4 ) p 2 5 / ( l e d 5 ) p 2 6 / ( l e d 6 ) p 2 7 / ( l e d 7 ) p 3 2 p 3 3 p 3 6 p 3 7 p 4 7 / s r d y 1 o e ] v s s v c c v p p s d a s c l k b u s y : c o n n e c t t o t h e c e r a m i c o s c i l l a t i o n c i r c u i t . i n d i c a t e s t h e f l a s h m e m o r y p i n . ]
101 3803/3804 group single-chip 8-bit cmos microcomputer mitsubishi microcomputers table 21 pin description (flash memory serial i/o mode) v cc , v ss cnv ss _____ reset x in x out av ss v ref p0 0 Cp0 7 p1 0 Cp1 7 p2 0 Cp2 7 p3 0 Cp3 6 p3 7 p4 0 Cp4 3 , p4 5 p4 4 p4 6 p4 7 p5 0 Cp5 7 p6 0 Cp6 7 pin power supply v pp input reset input clock input clock output analog supply input reference voltage input input port p0 input port p1 input port p2 input port p3 control signal input input port p4 sda i/o sclk input busy output input port p5 input port p6 name input input input output input input input input input input input i/o input output input input input /output functions supply 5 v 10 % to v cc and 0 v to v ss . connect to 11.7 v to 12.6 v. connect to v ss . connect a ceramic resonator between x in and x out . connect to v ss . input an arbitrary level between the range of v ss and v cc . input h or l, or keep them open. input h or l, or keep them open. input h or l, or keep them open. input h or l, or keep them open. __ oe input pin input h or l to p4 0 - p4 3 , p4 5 , or keep them open. this pin is for serial data i/o. this pin is for serial clock input. this pin is for busy signal output. input h or l, or keep them open. input h or l, or keep them open.
102 3803/3804 group single-chip 8-bit cmos microcomputer mitsubishi microcomputers functional outline (serial i/o mode) in the serial i/o mode, data is transferred synchronously with the clock using serial input/output. the input data is read from the sda pin into the internal circuit synchronously with the rising edge of the serial clock pulse; the output data is output from the sda pin synchronously with the falling edge of the serial clock pulse. data is transferred in units of eight bits. in the first transfer, the user inputs the command code. this is fol- lowed by address input and data input/output according to the contents of the command. table 22 shows the software com- mands used in the serial i/o mode. the following explains each software command. table 22 software command (serial i/o mode) read program program verify erase erase verify error check number of transfers command first command code input 00 16 40 16 c0 16 20 16 a0 16 80 16 read address l (input) program address l (input) verify data (output) 20 16 (input) verify address l (input) error code (output) second read address h (input) program address h (input) verify address h (input) third fourth read data (output) program data (input) verify data (output) l read command input command code 00 16 in the first transfer. proceed and input the low-order 8 bits and the high-order 8 bits of the address and __ pull the oe pin low. when this is done, the 3803/3804 group reads out the contents of the specified address, and then latchs it into __ the internal data latch. when the oe pin is released back high and serial clock is input to the sclk pin, the read data that has been latched into the data latch is serially output from the sda pin. fig. 93 timings during reading ? sclk busy oe sda t ch a 0 a 7 a 8 a 15 d 0 d 7 t ch t cr command code input (00 16 ) read address input (l) read address input (h) read data output t wr read t rc note : when outputting the read data, the sda pin is switched for output at the first falling edge of sclk. the sda pin is placed in the floating state during the period of th (c-e) after the last rising edge of sclk (at the 8th bit). 00000000
103 3803/3804 group single-chip 8-bit cmos microcomputer mitsubishi microcomputers l program command input command code 40 16 in the first transfer. proceed and input the low-order 8 bits and the high-order 8 bits of the address and then program data. programming is initiated at the last rising edge of the serial clock during program data transfer. the busy pin is driven high during program operation. programming is completed within 10 m s as measured by the internal timer, and the busy pin is pulled low. note : a programming operation is not completed by executing the program command once. always be sure to execute a pro- gram verify command after executing the program command. when the failure is found in the verification, the user must re- peatedly execute the program command until the pass in the verification. refer to figure 90 for the programming flowchart. l program verify command input command code c0 16 in the first transfer. proceed and drive __ the oe pin low. when this is done, the 3803/3804 group verify- reads the programmed addresss contents, and then latchs it into __ the internal data latch. when the oe pin is released back high and serial clock is input to the sclk pin, the verify data that has been latched into the data latch is serially output from the sda pin. fig. 95 timings during program verify fig. 94 timings during programming sclk busy oe sda t ch a 0 00000010 a 7 a 8 a 15 d 0 d 7 t ch t ch t pc command code input (40 16 ) program address input (l) program address input (h) program data input t wp program sclk busy oe sda d 0 d 7 t crpv command code input (c0 16 ) verify data output t wr verify read t rc note: when outputting the verify data, the sda pin is switched for output at the first falling edge of sclk. the sda pin is placed in the floating state during the period of th (c-e) after the last rising edge of sclk (at the 8th bit). 00000011 ?
104 3803/3804 group single-chip 8-bit cmos microcomputer mitsubishi microcomputers l erase command input command code 20 16 in the first transfer and command code 20 16 again in the second transfer. when this is done, the 3803/ 3804 group executes an erase command. erase is initiated at the last rising edge of the serial clock. the busy pin is driven high during the erase operation. erase is completed within 9.5 ms as measured by the internal timer, and the busy pin is pulled low. note that data 00 16 must be written to all memory locations before executing the erase command. note: a erase operation is not completed by executing the erase command once. always be sure to execute a erase verify command after executing the erase command. when the fail- ure is found in the verification, the user must repeatedly ex- ecute the erase command until the pass in the verification. refer to figure 90 for the erase flowchart. fig. 96 timings at erasing l erase verify command the user must verify the contents of all addresses after complet- ing the erase command. input command code a0 16 in the first transfer. proceed and input the low-order 8 bits and the high-order __ 8 bits of the address and pull the oe pin low. when this is done, the 3803/3804 group reads out the contents of the specified ad- __ dress, and then latchs it into the internal data latch. when the oe pin is released back high and serial clock is input to the sclk pin, the verify data that has been latched into the data latch is serially output from the sda pin. note: if any memory location where the contents have not been erased is found in the erase verify operation, execute the op- eration of erase ? erase verify over again. in this case, however, the user does not need to write data 00 16 to memory locations before erasing. fig. 97 timings during erase verify tw e sclk busy oe sda t ch t ec 00000100 00000100 command code input (20 16 ) command code input (20 16 ) erase ? ? sclk busy oe sda t ch a 0 a 7 a 8 a 15 d 0 d 7 t ch t crev command code input (a0 16 ) verify address input (l) verify address input (h) verify data output t wr verify read t rc note : when outputting the verify data, the sda pin is switched for output at the first falling edge of sclk. the sda pin is placed in the floating state during the period of th (c-e) after the last rising edge of sclk (at the 8th bit). 00000101
105 3803/3804 group single-chip 8-bit cmos microcomputer mitsubishi microcomputers l error check command input command code 80 16 in the first transfer, and the 3803/3804 group outputs error information from the sda pin, beginning at the next falling edge of the serial clock. if the lsb bit of the 8-bit error information is 1, it indicates that a command error has occurred. a command error means that some invalid commands other than commands shown in table 22 has been input. when a command error occurs, the serial communication circuit sets the corresponding flag and stops functioning to avoid an erro- neous programming or erase. when being placed in this state, the serial communication circuit does not accept the subsequent serial clock and data (even including an error check command). there- fore, if the user wants to execute an error check command, temporarily drop the v pp pin input to the v pp l level to terminate the serial input/output mode. then, place the 3803/3804 group into the serial i/o mode back again. the serial communication cir- cuit is reset by this operation and is ready to accept commands. the error flag alone is not cleared by this operation, so the user can examine the serial communication circuits error conditions before reset. this examination is done by the first execution of an error check command after the reset. the error flag is cleared when the user has executed the error check command. because the error flag is undefined immediately after power-on, always be sure to execute the error check command. fig. 98 timings at error checking sclk busy oe sda e0 t ch command code input (80 16 ) error flag output 00000001 ?????? note: when outputting the error flag, the sda pin is switched for output at the first falling edge of the serial clock. the sda pin i s placed in the floating state during the period of th (c-e) after the last rising edge of the serial clock (at the 8th bit). ? ? ?
106 3803/3804 group single-chip 8-bit cmos microcomputer mitsubishi microcomputers dc electrical characteristics (ta = 25 c, v cc = 5 v 10 %, v pp = 11.7 v to 12.6 v, unless otherwise noted) i cc , i pp -relevant standards during read, program, and erase are the same as in the parallel input/output mode. v ih , v il , v oh , v ol , i ih , and __ i il for the sclk, sda, busy, oe pins conform to the microcomputer modes. table 23 ac electrical characteristics (t a = 25 c, v cc = 5 v 10 %, v pp = 11.7 v to 12.6 v, f(x in ) = 10 mhz, unless otherwise noted) symbol max. 10 9.5 90 250 (note 4) t ch t cr t wr t rc t crpv t wp t pc t crev t we t ec t c(ck) t w(ckh) t w(ckl) t r(ck) t f(ck) t d(c-q) t h(c-q) t h(c-e) t su(d-c) t h(c-d) serial transmission interval read waiting time after transmission read pulse width transfer waiting time after read waiting time before program verify programming time transfer waiting time after programming waiting time before erase verify erase time transfer waiting time after erase sclk input cycle time sclk high-level pulse width sclk low-level pulse width sclk rise time sclk fall time sda output delay time sda output hold time sda output hold time (only the 8th bit) sda input set up time sda input hold time parameter ns ns ns ns m s m s ns ns ns ns ns ns ns ns ns ns ns ns ns ns unit min. 500 (note 1) 500 (note 1) 400 (note 2) 500 (note 1) 6 500 (note 1) 6 500 (note 1) 250 100 100 20 20 0 0 150 (note 3) 30 90 limits notes 1: when f(x in ) = 10 mhz or less, calculate the minimum value according to formula 1. formula 1 : 10 6 2: when f(x in ) = 10 mhz or less, calculate the minimum value according to formula 2. formula 2 : 10 6 3: when f(x in ) = 10 mhz or less, calculate the minimum value according to formula 3. formula 3 : 10 6 4: when f(x in ) = 10 mhz or less, calculate the minimum value according to formula 4 formula 4 : 10 6 5000 f(x in ) 4000 f(x in ) 2500 f(x in ) 1500 f(x in ) ac waveforms sclk sda input test conditions for ac characteristics ?output timing voltage : v ol = 0.8 v, v oh = 2.0 v ?input timing voltage : v il = 0.2 v cc , v ih = 0.8 v cc sda output t c(ck) t r(ck) t d(c-q) t su(d-c) t h(c-d) t h(c-e) t h(c-q) t f(ck) t w(ckl) t w(ckh)
107 3803/3804 group single-chip 8-bit cmos microcomputer mitsubishi microcomputers (3) flash memory mode 3 (cpu reprogramming mode) the 3803/3804 group has the cpu reprogramming mode where a built-in flash memory is handled by the central processing unit (cpu). in cpu reprogramming mode, the flash memory is handled by writing and reading to/from the flash memory control register (see figure 99) and the flash command register (see figure 100). the cnv ss pin is used as the v pp power supply pin in cpu repro- gramming mode. it is necessary to apply the power-supply voltage of v pp h from the external to this pin. functional outline (cpu reprogramming mode) figure 99 shows the structure of the flash memory control register. figure 100 shows the structure of the flash command register. bit 0 of the flash memory control register is the cpu reprogram- ming mode select bit. when this bit is set to 1 and v pp h is applied to the cnvss/v pp pin, the cpu reprogramming mode is selected. whether the cpu reprogramming mode is realized or not is judged by reading the cpu reprogramming mode monitor flag (bit 2 of the flash memory control register). bit 1 is a busy flag which becomes 1 during erase and program execution. whether these operations have been completed or not is judged by checking this flag after each command of erase and the pro- gram is executed. bits 4, 5 of the flash memory control register are the erase/pro- gram area select bits. these bits specify an area where erase and program is operated. when the erase command is executed after an area is specified by these bits, only the specified area is erased. only for the specified area, programming is enabled; for the other areas, programming is disabled. figure 101 shows the structure of the cpu mode register in the cpu reprogramming mode. set bit 1 to 0 (single-chip or memory expansion mode) in the cpu reprogramming mode. fig. 99 structure of flash memory control register 76543210 0 0 flash memory control regsiter (fcon : address 0ffe 16 ) cpu reprogramming mode select bit (notes 1, 2) 0 : cpu reprogramming mode is invalid. (normal operation mode) 1 : when applying 0 v or v pp l to cnv ss /v pp pin, cpu reprogramming mode is invalid. when applying v pp h to cnv ss /v pp pin, cpu reprogramming mode is valid. erase/program busy flag 0 : erase and program are completed or not have been executed. 1 : erase/program is being executed. cpu reprogramming mode monitor flag 0 : cpu reprogramming mode is invalid. 1 : cpu reprogramming mode is valid. erase/program area select bits 0 0 : addresses 1000 16 to ffff 16 (total 60 kbytes) 0 1 : addresses 1000 16 to 7fff 16 (total 28 kbytes) 1 0 : addresses 8000 16 to ffff 16 (total 32 kbytes) 1 1 : not available fix this bit to ?. fix this bit to ?. notes 1: bit 0 can be reprogrammed only when 0 v is applied to the cnv ss /v pp pin. 2: when bit 0 is ?,?the processor mode does not change even if v pp h is applied to the cnv ss /v pp pin. not used (returns "0" when read)
108 3803/3804 group single-chip 8-bit cmos microcomputer mitsubishi microcomputers l cpu reprogramming mode operation procedure the operation procedure in cpu reprogramming mode is de- scribed below. < beginning procedure > apply 0 v to the cnvss/v pp pin for reset release. set the cpu mode register (see figure 101). a after cpu reprogramming mode control program is transferred to internal ram, jump to this control program on ram. (the follow- ing operations are controlled by this control program). ? set 1" to the cpu reprogramming mode select bit. ? apply v pp h to the cnv ss /v pp pin. ? wait till cnv ss /v pp pin becomes 12v. d read the cpu reprogramming mode monitor flag to confirm whether the cpu reprogramming mode is valid. ? the operation of the flash memory is executed by software-com- mand-writing to the flash command register . note: the following are necessary other than this: ?control for data which is input from the external (serial i/o etc.) and to be programmed to the flash memory ?initial setting for ports etc. ?writing to the watchdog timer < release procedure > apply 0 v to the cnv ss /v pp pin. wait till cnv ss /v pp pin becomes 0 v. a set the cpu reprogramming mode select bit to 0. each software command is explained as follows. l read command when 00 16 " is written to the flash command register, the 3803/ 3804 group enters the read mode. the contents of the corre- sponding address can be read by reading the flash memory (for instance, with the lda instruction etc.) under this condition. the read mode is maintained until another command code is written to the flash command register. accordingly, after setting the read mode once, the contents of the flash memory can continuously be read. after reset and after the reset command is executed, the read mode is set. fig. 100 structure of flash command register fig. 101 structure of cpu mode register in cpu rewriting mode writing of software command ?0 16 ?0 16 ?0 16 ?0 16 ?+ ?0 16 ?0 16 ?f 16 ?+ ?f 16 ?read command ?program command ?program verify command ?erase command ?erase verify command ?reset command note: the flash command register is write-only register. flash command register (fcmd : address 0fff 16 ) 76 5 4 3 2 1 0 c p u m o d e r e g i s t e r ( c p u m : a d d r e s s 0 0 3 b 1 6 ) b 7 b 0 s t a c k p a g e s e l e c t i o n b i t 0 : 0 p a g e 1 : 1 p a g e r e s e r v e d ( d o n o t w r i t e 0 t o t h i s b i t w h e n u s i n g x c i n x c o u t o s c i l l a t i o n f u n c t i o n . ) p r o c e s s o r m o d e b i t s b 1 b 0 0 0 : s i n g l e - c h i p m o d e 0 1 : m e m o r y e x p a n s i o n m o d e 1 x : n o t a v a i l a b l e p o r t x c s w i t c h b i t 0 : i / o p o r t f u n c t i o n ( s t o p o s c i l l a t i n g ) 1 : x c i n x c o u t o s c i l l a t i n g f u n c t i o n m a i n c l o c k ( x i n x o u t ) s t o p b i t 0 : o s c i l l a t i n g 1 : s t o p p e d m a i n c l o c k d i v i s i o n r a t i o s e l e c t i o n b i t s b 7 b 6 0 0 : f = f ( x i n ) / 2 ( h i g h - s p e e d m o d e ) 0 1 : f = f ( x i n ) / 8 ( m i d d l e - s p e e d m o d e ) 1 0 : f = f ( x c i n ) / 2 ( l o w - s p e e d m o d e ) 1 1 : n o t a v a i l a b l e 0
109 3803/3804 group single-chip 8-bit cmos microcomputer mitsubishi microcomputers l program command when 40 16 is written to the flash command register, the 3803/ 3804 group enters the program mode. subsequently to this, if the instruction (for instance, sta or ldm instruction) for writing byte data in the address to be programmed is executed, the control circuit of the flash memory executes the program. the erase/program busy flag of the flash memory control register is set to 1 when the program starts, and becomes 0" when the program is completed. accordingly, after the write in- struction is executed, cpu can recognize the completion of the program by polling this bit. the programmed area must be specified beforehand by the erase/ program area select bits. during programming, watchdog timer stops with ffff 16 set. note: a programming operation is not completed by executing the program command once. always be sure to execute a pro- gram verify command after executing the program command. when the failure is found in this verification, the user must re- peatedly execute the program command until the pass. refer to figure 102 for the flow chart of the programming. l program verify command when c0 16 " is written to the flash command register, the 3803/ 3804 group enters the program verify mode. subsequently to this, if the instruction (for instance, lda instruction) for reading byte data from the address to be verified (i.e., previously programmed address), the contents which has been written to the address ac- tually is read. cpu compares this read data with data which has been written by the previous program command. in consequence of the compari- son, if not agreeing, the operation of program ? program verify must be executed again. l erase command when writing 20 16 twice continuously to the flash command reg- ister, the flash memory control circuit performs erase to the area specified beforehand by the erase/program area select bits. erase/program busy flag of the flash memory control register be- comes 1 when erase begins, and it becomes 0" when erase completes. accordingly, cpu can recognize the completion of erase by polling this bit. data 00 16 must be written to all areas to be erased by the pro- gram and the program verify commands before the erase command is executed. during erasing, watchdog timer stops with ffff 16 set. note: the erasing operation is not completed by executing the erase command once. always be sure to execute an erase verify command after executing the erase command. when the fail- ure is found in this verification, the user must repeatedly ex- ecute the erase command until the pass. refer to figure 102 for the erasing flowchart. l erase verify command when a0 16 " is written to the flash command register, the 3803/ 3804 group enters the erase verify mode. subsequently to this, if the instruction (for instance, lda instruction) for reading byte data from the address to be verified, the contents of the address is read. cpu must erase and verify to all erased areas in a unit of ad- dress. if the address of which data is not ff 16 " (i.e., data is not erased) is found, it is necessary to discontinue erasure verification there, and execute the operation of erase ? erase verify again. note: by executing the operation of erase ? erase verify again when the memory not erased is found. it is unnecessary to write data 00 16 before erasing in this case. l reset command the reset command is a command to discontinue the program or erase command on the way. when ff 16 is written to the command register two times continuously after 40 16 or 20 16 is written to the flash command register, the program, or erase command becomes invalid (reset), and the 3803/3804 group enters the reset mode. the contents of the memory does not change even if the reset com- mand is executed. dc electric characteristics note: the characteristic concerning the flash memory part are the same as the characteristic of the parallel i/o mode. ac electric characteristics note: the characteristics are the same as the characteristic of the microcomputer mode.
110 3803/3804 group single-chip 8-bit cmos microcomputer mitsubishi microcomputers fig. 102 flowchart of program/erase operation at cpu reprogramming mode erase program busy flag = 0 start adrs = first location x = 0 write program command write program data wait 1 m s x = x + 1 write program-verify command 40 16 din c0 16 00 16 duration = 6 m s x = 25 ? last adrs ? no inc adrs write read command device passed device failed verify byte ? verify byte ? fail fail program erase yes yes no pass pass start adrs = first location x = 0 write erase command program all bytes = 00 16 all bytes = 00 16 ? write erase command x = x + 1 write erase-verify command 20 16 20 16 a0 16 00 16 duration = 6 m s x = 1000 ? last adrs ? no inc adrs write read command device passed device failed verify byte ? verify byte ? fail fail yes yes no pass pass yes no erase program busy flag = 0 wait 1 m s no yes yes no
111 3803/3804 group single-chip 8-bit cmos microcomputer mitsubishi microcomputers notes on programming processor status register the contents of the processor status register (ps) after a reset are undefined, except for the interrupt disable flag (i) which is 1. af- ter a reset, initialize flags which affect program execution. in particular, it is essential to initialize the index x mode (t) and the decimal mode (d) flags because of their effect on calculations. interrupts the contents of the interrupt request bits do not change immedi- ately after they have been written. after writing to an interrupt request register, execute at least one instruction before perform- ing a bbc or bbs instruction. decimal calculations ? to calculate in decimal notation, set the decimal mode flag (d) to 1, then execute an adc or sbc instruction. after executing an adc or sbc instruction, execute at least one instruction be- fore executing a sec, clc, or cld instruction. ? in decimal mode, the values of the negative (n), overflow (v), and zero (z) flags are invalid. timers if a value n (between 0 and 255) is written to a timer latch, the fre- quency division ratio is 1/(n+1). multiplication and division instructions ? the index x mode (t) and the decimal mode (d) flags do not af- fect the mul and div instruction. ? the execution of these instructions does not change the con- tents of the processor status register. ports the contents of the port direction registers cannot be read. the following cannot be used: ? the data transfer instruction (lda, etc.) ? the operation instruction when the index x mode flag (t) is 1 ? the instruction with the addressing mode which uses the value of a direction register as an index ? the bit-test instruction (bbc or bbs, etc.) to a direction register ? the read-modify-write instructions (ror, clb, or seb, etc.) to a direction register. use instructions such as ldm and sta, etc., to set the port direc- tion registers. serial i/o in clock synchronous serial i/o, if the receive side is using an ex- ternal clock and it is to output the s rdy signal, set the transmit enable bit, the receive enable bit, and the s rdy output enable bit to 1. serial i/o continues to output the final bit from the t x d pin after transmission is completed. s out2 pin for serial i/o2 goes to high impedance after transfer is completed. when in serial i/os 1 and 3 (clock-synchronous mode) or in serial i/o2, an external clock is used as synchronous clock, write trans- mission data to the transmit buffer register or serial i/o2 register, during transfer clock is h. a-d converter the comparator uses capacitive coupling amplifier whose charge will be lost if the clock frequency is too low. therefore, make sure that f(x in ) is at least on 500 khz during an a-d conversion. do not execute the stp or wit instruction during an a-d conver- sion. d-a converter the accuracy of the d-a converter becomes rapidly poor under the v cc = 4.0 v or less condition; a supply voltage of v cc 3 4.0 v is recommended. when a d-a converter is not used, set all values of d-ai conversion registers (i=1, 2) to 00 16 . instruction execution time the instruction execution time is obtained by multiplying the pe- riod of the internal clock f by the number of cycles needed to execute an instruction. the number of cycles required to execute an instruction is shown in the list of machine instructions. the period of the internal clock f is half of the x in period in high- speed mode.
112 3803/3804 group single-chip 8-bit cmos microcomputer mitsubishi microcomputers notes on usage handling of power source pins in order to avoid a latch-up occurrence, connect a capacitor suit- able for high frequencies as bypass capacitor between power source pin (v cc pin) and gnd pin (v ss pin), and between power source pin (v cc pin) and analog power source input pin (av ss pin). besides, connect the capacitor to as close as possible. for bypass capacitor which should not be located too far from the pins to be connected, a ceramic capacitor of 0.01 m fC0.1 m f is recom- mended. flash memory version the cnv ss pin is connected to the internal memory circuit block by a low-ohmic resistance, since it has the multiplexed function to be a programmable power source pin (v pp pin) as well. to improve the noise reduction, connect a track between cnv ss pin and v ss pin or v cc pin with 1 to 10 k w resistance. the mask rom version track of cnv ss pin has no operational in- terference even if it is connected to vss pin or vcc pin via a resistor. data required for mask orders the following are necessary when ordering a mask rom produc- tion: 1.mask rom confirmation form 2.mark specification form 3.data to be written to rom, in eprom form (three identical cop- ies)
113 3803/3804 group single-chip 8-bit cmos microcomputer mitsubishi microcomputers electrical characteristics table 24 absolute maximum ratings power source voltage s input voltage p0 0 Cp0 7 , p1 0 Cp1 7 , p2 0 Cp2 7 , p3 0 , p3 1 , p3 4 Cp3 7 , p4 0 Cp4 7 , p5 0 Cp5 7 , p6 0 Cp6 7 , v ref input voltage p3 2 , p3 3 input voltage reset, x in input voltage cnv ss (mask rom version) input voltage cnv ss (flash memory version) output voltage p0 0 Cp0 7 , p1 0 Cp1 7 , p2 0 Cp2 7 , p3 0 , p3 1 , p3 4 Cp3 7 , p4 0 Cp4 7 , p5 0 Cp5 7 , p6 0 Cp6 7 , x out output voltage p3 2 , p3 3 power dissipation operating temperature storage temperature v cc v i v i v i v i v i v o v o p d t opr t stg symbol parameter conditions ratings C0.3 to 6.5 C0.3 to v cc +0.3 C0.3 to 5.8 C0.3 to v cc +0.3 C0.3 to v cc +0.3 C0.3 to 13 C0.3 to v cc +0.3 C0.3 to 5.8 1000 (note) C20 to 85 C65 to 125 v v v v v v v v mw c c unit t a = 25 c all voltages are based on v ss . output transistors are cut off. note: in flat package, this value is 300 mv.
114 3803/3804 group single-chip 8-bit cmos microcomputer mitsubishi microcomputers 5.5 5.5 5.5 5.5 v cc v cc v cc v cc 5.5 5.5 5.5 v cc 0.2v cc 0.3v cc 0.6 0.2v cc 0.16 v cc power source voltage (f(x in ) 8.4 mhz) power source voltage (f(x in ) 12.5 mhz) power source voltage (f(x in ) 16.8 mhz) power source voltage (flash memory version) power source voltage analog reference voltage (when a-d converter is used) analog reference voltage (when d-a converter is used) analog power source voltage analog input voltage an 0 Can 15 h input voltage p0 0 Cp0 7 , p1 0 Cp1 7 , p2 0 Cp2 7 , p3 0 , p3 3 , p3 4 Cp3 7 , p4 0 Cp4 7 , p5 0 Cp5 7 , p6 0 Cp6 7 h input voltage p3 2 , p3 3 h input voltage (when i 2 c-bus input level is selected) s da , s cl h input voltage (when smbus input level is selected) s da , s cl h input voltage reset, x in , x cin , cnv ss l input voltage p0 0 Cp0 7 , p1 0 Cp1 7 , p2 0 Cp2 7 , p3 0 Cp3 7 , p4 0 Cp4 7 , p5 0 Cp5 7 , p6 0 Cp6 7 l input voltage (when i 2 c-bus input level is selected) s da , s cl l input voltage (when smbus input level is selected) s da , s cl l input voltage reset, cnv ss l input voltage x in , x cin v cc v cc v ss v ref av ss v ia v ih v ih v ih v ih v ih v il v il v il v il v il symbol parameter limits min. v v v v v v v v v v v v v v v v v unit table 25 recommended operating conditions (v cc = 2.7 to 5.5 v, t a = C20 to 85 c, unless otherwise noted) 2.7 4.0 4.5 4.0 2.0 2.7 av ss 0.8v cc 0.8v cc 0.7v cc 1.4 0.8v cc 0 0 0 5.0 5.0 5.0 5.0 0 0 typ. max.
115 3803/3804 group single-chip 8-bit cmos microcomputer mitsubishi microcomputers table 26 recommended operating conditions (v cc = 2.7 to 5.5 v, t a = C20 to 85 c, unless otherwise noted) C80 C80 80 80 80 C40 C40 40 40 40 C10 10 20 C5 5 10 16.8 50 h total peak output current p0 0 Cp0 7 , p1 0 Cp1 7 , p2 0 Cp2 7 , p3 0 , p3 1 , p3 4 Cp3 7 (note 1) h total peak output current p4 0 Cp4 7 , p5 0 Cp5 7 , p6 0 Cp6 7 (note 1) l total peak output current p0 0 Cp0 7 , p1 0 Cp1 7 , p3 0 Cp3 7 (note 1) l total peak output current p2 0 Cp2 7 (note 1) l total peak output current p4 0 Cp4 7 ,p5 0 Cp5 7 , p6 0 Cp6 7 (note 1) h total average output current p0 0 Cp0 7 , p1 0 Cp1 7 , p2 0 Cp2 7 , p3 0 , p3 1 , p3 4 Cp3 7 (note 1) h total average output current p4 0 Cp4 7 ,p5 0 Cp5 7 , p6 0 Cp6 7 (note 1) l total average output current p0 0 Cp0 7 , p1 0 Cp1 7 , p3 0 Cp3 7 (note 1) l total average output current p2 0 Cp2 7 (note 1) l total average output current p4 0 Cp4 7 ,p5 0 Cp5 7 , p6 0 Cp6 7 (note 1) h peak output current p0 0 Cp0 7 , p1 0 Cp1 7 , p2 0 Cp2 7 , p3 0 . p3 1 , p3 4 Cp3 7 , p4 0 Cp4 7 , p5 0 Cp5 7 , p6 0 Cp6 7 (note 2) l peak output current p0 0 Cp0 7 , p1 0 Cp1 7 , p3 0 Cp3 7 , p4 0 Cp4 7 , p5 0 Cp5 7 , p6 0 Cp6 7 (note 2) l peak output current p2 0 Cp2 7 (note 2) h average output current p0 0 Cp0 7 , p1 0 Cp1 7 , p2 0 Cp2 7 , p3 0 , p3 1, p3 4 Cp3 7 , p4 0 Cp4 7 , p5 0 Cp5 7 , p6 0 Cp6 7 (note 3) l average output current p0 0 Cp0 7 , p1 0 Cp1 7 , p3 0 Cp3 7 , p4 0 Cp4 7 , p5 0 Cp5 7 , p6 0 Cp6 7 (note 3) l average output current p2 0 Cp2 7 (note 3) main clock input oscillation frequency (note 4) sub-clock input oscillation frequency (notes 4, 5) s i oh(peak) s i oh(peak) s i ol(peak) s i ol(peak) s i ol(peak) s i oh(avg) s i oh(avg) s i ol(avg) s i ol(avg) s i ol(avg) i oh(peak) i ol(peak) i ol(peak) i oh(avg) i ol(avg) i ol(avg) f(x in ) f(x cin ) symbol parameter limits min. ma ma ma ma ma ma ma ma ma ma ma ma ma ma ma ma mhz mhz mhz khz unit typ. max. notes 1: the total output current is the sum of all the currents flowing through all the applicable ports. the total average current is an aver- age value measured over 100 ms. the total peak current is the peak value of all the currents. 2: the peak output current is the peak current flowing in each port. 3: the average output current i ol (avg), i oh (avg) are average value measured over 100 ms. 4: when the oscillation frequency has a duty cycle of 50%. 5: when using the microcomputer in low-speed mode, set the sub-clock input oscillation frequency on condition that f(x cin ) < f(x in )/3. vcc = 4.5C5.5 v vcc = 4.0C4.5 v vcc = 2.7C4.0 v 8.6vccC21,9 41 13 vccC 3 26 32.768
116 3803/3804 group single-chip 8-bit cmos microcomputer mitsubishi microcomputers table 27 electrical characteristics (v cc = 2.7 to 5.5 v, v ss = 0 v, t a = C20 to 85 c, unless otherwise noted) h output voltage p0 0 Cp0 7 , p1 0 Cp1 7 , p2 0 Cp2 7 p3 0 , p3 1 , p3 4 Cp3 7 , p4 0 Cp4 7 , p5 0 Cp5 7 , p6 0 Cp6 7 (note 1) l output voltage p0 0 Cp0 7 , p1 0 Cp1 7 , p2 0 Cp2 7 p3 0 Cp3 7 , p4 0 Cp4 7 , p5 0 Cp5 7 p6 0 Cp6 7 hysteresis cntr 0 , cntr 1 , cntr 2 , int 0 Cint 4 hysteresis rxd1, s clk1 , s in2 , s clk2 , rxd3, s clk3 hysteresis reset h input current p0 0 Cp0 7 , p1 0 Cp1 7 , p2 0 Cp2 7 p3 0 Cp3 7 , p4 0 Cp4 7 , p5 0 Cp5 7 p6 0 Cp6 7 h input current reset, cnv ss h input current x in l input current p0 0 Cp0 7 , p1 0 Cp1 7 , p2 0 Cp2 7 , p3 0 Cp3 7 , p4 0 Cp4 7 , p5 0 Cp5 7 , p6 0 Cp6 7 l input current reset,cnv ss l input current x in l input current (at pull-up) p0 0 Cp0 7 , p1 0 Cp1 7 , p2 0 Cp2 7 , p3 0 , p3 1 , p3 4 Cp3 7 , p4 0 Cp4 7 , p5 0 Cp5 7 , p6 0 Cp6 7 ram hold voltage limits v v v v v v v m a m a m a m a m a m a m a m a v parameter min. typ. max. symbol unit note 1: p3 5 is measured when the p3 5 /txd 3 p-channel output disable bit of the uart3 control register (bit 4 of address 0033 16 ) is 0. p4 5 is measured when the p4 5 /txd 1 p-channel output disable bit of the uart1 control register (bit 4 of address 001b 16 ) is 0. i oh = C10 ma v cc = 4.0C5.5 v i oh = C1.0 ma v cc = 2.7C5.5 v i ol = 10 ma v cc = 4.0C5.5 v i ol = 1.6 ma v cc = 2.7C5.5 v v i = v cc (pin floating. pull-up transistors off) v i = v cc v i = v cc v i = v ss (pin floating. pull-up transistors off) v i = v ss v i = v ss v i = v ss v cc = 5.0 v v i = v ss v cc = 3.0 v when clock stopped v cc C2.0 v cc C1.0 C80 C30 2.0 test conditions 0.4 0.5 0.5 4 C4 C210 C70 2.0 0.4 5.0 5.0 C5.0 C5.0 C420 C140 5.5 v oh v ol v t+ Cv tC v t+ Cv tC v t+ Cv tC i ih i ih i ih i il i il i il i il v ram
117 3803/3804 group single-chip 8-bit cmos microcomputer mitsubishi microcomputers table 28 electrical characteristics (flash memory version) (v cc = 2.7 to 5.5 v, v ss = 0 v, t a = C20 to 85 c, unless otherwise noted) power source current limits parameter min. typ. max. symbol unit high-speed mode f(x in ) = 16.8 mhz f(x cin ) = 32.768 khz output transistors off high-speed mode f(x in ) = 12.5 mhz f(x cin ) = 32.768 khz output transistors off high-speed mode f(x in ) = 8.4 mhz f(x cin ) = 32.768 khz output transistors off high-speed mode f(x in ) = 16.8 mhz (in wit state) f(x cin ) = 32.768 khz output transistors off low-speed mode f(x in ) = stopped f(x cin ) = 32.768 khz output transistors off low-speed mode f(x in ) = stopped f(x cin ) = 32.768 khz (in wit state) output transistors off low-speed mode (v cc = 3 v) f(x in ) = stopped f(x cin ) = 32.768 khz output transistors off low-speed mode (v cc = 3 v) f(x in ) = stopped f(x cin ) = 32.768 khz (in wit state) output transistors off middle-speed mode f(x in ) = 16.8 mhz f(x cin ) = stopped output transistors off middle-speed mode f(x in ) = 16.8 mhz (in wit state) f(x cin ) = stopped output transistors off increment when a-d conversion is executed f(x in ) = 16.8 mhz all oscillation stopped (in stp state) output transistors off test conditions 22 18 13.5 6 200 60 55 20.0 12 5.5 1.0 10 i cc ta = 25 c ta = 85 c 12 10 7 3.5 60 30 20 8.0 6 3 500 0.1 ma ma ma ma m a m a m a m a ma ma m a m a m a
118 3803/3804 group single-chip 8-bit cmos microcomputer mitsubishi microcomputers table 29 electrical characteristics (mask rom version) (v cc = 2.7 to 5.5 v, v ss = 0 v, t a = C20 to 85 c, unless otherwise noted) power source current limits parameter min. typ. max. symbol unit high-speed mode f(x in ) = 16.8 mhz f(x cin ) = 32.768 khz output transistors off high-speed mode f(x in ) = 12.5 mhz f(x cin ) = 32.768 khz output transistors off high-speed mode f(x in ) = 8.4 mhz f(x cin ) = 32.768 khz output transistors off high-speed mode f(x in ) = 16.8 mhz (in wit state) f(x cin ) = 32.768 khz output transistors off low-speed mode f(x in ) = stopped f(x cin ) = 32.768 khz output transistors off low-speed mode f(x in ) = stopped f(x cin ) = 32.768 khz (in wit state) output transistors off low-speed mode (v cc = 3 v) f(x in ) = stopped f(x cin ) = 32.768 khz output transistors off low-speed mode (v cc = 3 v) f(x in ) = stopped f(x cin ) = 32.768 khz (in wit state) output transistors off middle-speed mode f(x in ) = 16.8 mhz f(x cin ) = stopped output transistors off middle-speed mode f(x in ) = 16.8 mhz (in wit state) f(x cin ) = stopped output transistors off increment when a-d conversion is executed f(x in ) = 16.8 mhz all oscillation stopped (in stp state) output transistors off test conditions 15 12 9 3.6 200 70 40 15 7 3.3 1.0 10 i cc ta = 25 c ta = 85 c 8 6.5 5 2 55 40 15 8 4 1.8 500 0.1 ma ma ma ma m a m a m a m a ma ma m a m a m a
119 3803/3804 group single-chip 8-bit cmos microcomputer mitsubishi microcomputers bit lsb 2tc(x in ) k w m a m a m a resolution absolute accuracy (excluding quantization error) conversion time ladder resistor reference power source input current a-d port input current min. 12 50 typ. 35 150 max. 10 4 61 100 200 5 5.0 v cc = v ref = 5.0 v v ref = 5.0 v v ref = 5.0 v table 30 a-d converter characteristics (1) (v cc = 2.7 to 5.5 v, v ref = 2.0 v to v cc , v ss = av ss = 0 v, t a = C20 to 85 c, unless otherwise noted) 10-bit a-d mode (when conversion mode selection bit (bit 7 of address 0038 16 ) is 0) unit limits parameter C C t conv r ladder i vref i i(ad) test conditions at a-d converter operated at a-d converter stopped note 1: using one d-a converter, with the value in the d-a conversion register of the other d-a converter being 00 16 . t able 31 a-d converter characteristics (2) (v cc = 2.7 to 5.5 v, v ref = 2.0 v to v cc , v ss = av ss = 0 v, t a = C20 to 85 c, unless otherwise noted) 8-bit a-d mode (when conversion mode selection bit (bit 7 of address 0038 16 ) is 1) table 32 d-a converter characteristics (v cc = 2.7 to 5.5 v, v ref = 2.7 v to v cc , v ss = av ss = 0 v, t a = C20 to 85 c, unless otherwise noted) symbol bit lsb 2tc(x in ) k w m a m a m a resolution absolute accuracy (excluding quantization error) conversion time ladder resistor reference power source input current a-d port input current min. 12 50 typ. 35 150 max. 8 2 50 100 200 5 5.0 v cc = v ref = 5.0 v v ref = 5.0 v v ref = 5.0 v unit limits parameter C C t conv r ladder i vref i i(ad) test conditions at a-d converter operated at a-d converter stopped symbol bits % % m s k w ma resolution absolute accuracy setting time output resistor reference power source input current (note 1) min. 1 typ. 2.5 max. 8 1.0 2.5 3 4 3.2 unit limits parameter C C tsu ro i vref test conditions v cc = 4.0C5.5 v v cc = 2.7C4.0 v symbol
120 3803/3804 group single-chip 8-bit cmos microcomputer mitsubishi microcomputers timing requirements table 33 timing requirements (1) (v cc = 4.0 to 5.5 v, v ss = 0 v, t a = C20 to 85 c, unless otherwise noted) reset input l pulse width main clock input cycle time (vcc = 4.5C5.5 v) main clock input cycle time (vcc = 4.0C4.5 v) main clock input h pulse width (vcc = 4.5C5.5 v) main clock input h pulse width (vcc = 4.0C4.5 v) main clock input l pulse width (vcc = 4.5C5.5 v) main clock input l pulse width (vcc = 4.0C4.5 v) sub-clock input cycle time sub-clock input h pulse width sub-clock input l pulse width cntr 0 Ccntr 2 input cycle time cntr 0 Ccntr 2 input h pulse width cntr 0 Ccntr 2 input l pulse width int 00 , int 01 , int 1, int 2, int 3, int 40 , int 41 input h pulse width int 00 , int 01 , int 1, int 2, int 3, int 40 , int 41 input l pulse width serial i/o1, serial i/o3 clock input cycle time (note) serial i/o1, serial i/o3 clock input h pulse width (note) serial i/o1, serial i/o3 clock input l pulse width (note) serial i/o1, serial i/o3 input setup time serial i/o1, serial i/o3 input hold time serial i/o2 clock input cycle time serial i/o2 clock input h pulse width serial i/o2 clock input l pulse width serial i/o2 input setup time serial i/o2 input hold time t w (reset) t c (x in ) t wh (x in ) t wl (x in ) t c (x cin ) t wh (x cin ) t wl (x cin ) t c (cntr) t wh (cntr) t wl (cntr) t wh (int) t wl (int) t c (s clk1 ), t c (s clk3 ) t wh (s clk1 ), t wh (s clk3 ) t wl (s clk1 ), t wl (s clk3 ) t su (r x d1-s clk1 ), t su (r x d3-s clk3 ) t h (s clk1 -r x d1), t h (s clk1 -r x d3) t c (s clk2 ) t wh (s clk2 ) t wl (s clk2 ) t su (s in2 -s clk2 ) t h (s clk2 -s in2 ) limits m s ns ns ns ns ns ns m s m s m s ns parameter min. 2 59.5 10000 86vccC219 25 4000 86vccC219 25 4000 86vccC219 20 5 5 200 80 80 80 80 800 370 370 220 100 1000 400 400 200 200 typ. max. symbol unit note : when bit 6 of address 001a 16 is 1 (clock synchronous). divide this value by four when bit 6 of address 001a 16 and bit 6 of address 0032 16 are 0 (uart). ns ns ns ns ns ns ns ns ns ns ns ns ns ns
121 3803/3804 group single-chip 8-bit cmos microcomputer mitsubishi microcomputers table 34 timing requirements (2) (v cc = 2.7 to 4.0 v, v ss = 0 v, t a = C20 to 85 c, unless otherwise noted) reset input l pulse width main clock input cycle time main clock input h pulse width main clock input l pulse width sub-clock input cycle time sub-clock input h pulse width sub-clock input l pulse width cntr 0 Ccntr 2 input cycle time cntr 0 Ccntr 2 input h pulse width cntr 0 Ccntr 2 input l pulse width int 00 , int 01, int 1, int 2, int 3, int 40 , int 41 input h pulse width int 00 , int 01, int 1, int 2, int 3, int 40 , int 41 input l pulse width serial i/o1, serial i/o3 clock input cycle time (note) serial i/o1, serial i/o3 clock input h pulse width (note) serial i/o1, serial i/o3 clock input l pulse width (note) serial i/o1, serial i/o3 input setup time serial i/o1, serial i/o3 input hold time serial i/o2 clock input cycle time serial i/o2 clock input h pulse width serial i/o2 clock input l pulse width serial i/o2 input setup time serial i/o2 input hold time t w (reset) t c (x in ) t wh (x in ) t wl (x in ) t c (x cin ) t wh (x cin ) t wl (x cin ) t c (cntr) t wh (cntr) t wl (cntr) t wh (int) t wl (int) t c (s clk1 ), t c (s clk3 ) t wh (s clk1 ), t wh (s clk3 ) t wl (s clk1 ), t wl (s clk3 ) t su (r x d1-s clk1 ), t su (r x d3-s clk3 ) t h (s clk1 -r x d1), t h (s clk1 -r x d3) t c (s clk2 ) t wh (s clk2 ) t wl (s clk2 ) t su (s in2 -s clk2 ) t h (s clk2 -s in2 ) limits m s ns ns ns m s m s m s ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns parameter min. 2 26 5 10 3 82v cc C3 10000 82 v cc C3 10000 82 v cc C3 20 5 5 500 230 230 230 230 2000 950 950 400 200 2000 950 950 400 300 typ. max. symbol unit note : when bit 6 of address 001a 16 is 1 (clock synchronous). divide this value by four when bit 6 of address 001a 16 is 0 (uart).
122 3803/3804 group single-chip 8-bit cmos microcomputer mitsubishi microcomputers table 35 switching characteristics 1 (v cc = 4.0 to 5.5 v, v ss = 0 v, t a = C20 to 85 c, unless otherwise noted) serial i/o1, serial i/o3 clock output h pulse width serial i/o1, serial i/o3 clock output l pulse width serial i/o1, serial i/o3 output delay time (note 1) serial i/o1, serial i/o3 output valid time (note 1) serial i/o1, serial i/o3 clock output rising time serial i/o1, serial i/o3 clock output falling time serial i/o2 clock output h pulse width serial i/o2 clock output l pulse width serial i/o2 output delay time serial i/o2 output valid time serial i/o2 clock output falling time cmos output rising time (note 2) cmos output falling time (note 2) t wh (s clk1 ), t wh (s clk3 ) t wl (s clk1 ), t wl (s clk3 ) t d (s clk1 -t x d1) , t d (s clk3 -t x d3) t v (s clk1 -t x d1) , t v (s clk3 -t x d3) t r (s clk1 ) , t r (s clk3 ) t f (s clk1 ), t f (s clk3 ) t wh (s clk2 ) t wl (s clk2 ) t d (s clk2 -s out2 ) t v (s clk2 -s out2 ) t f (s clk2 ) t r (cmos) t f (cmos) limits ns ns ns ns ns ns ns ns ns ns ns ns ns parameter min. t c (s clk1 )/2C30 t c (s clk1 )/2C30 C30 t c (s clk2 )/2C160 t c (s clk2 )/2C160 0 typ. 10 10 max. 140 30 30 200 30 30 30 symbol unit notes 1: when the p4 5 /t x d1 p-channel output disable bit of the uart1 control register (bit 4 of address 001b 16 ) is 0. when the p3 5 /t x d3 p-channel output disable bit of the uart3 control register (bit 4 of address 0033 16 ) is 0. 2: the x out pin is excluded. test conditions fig. 65 table 36 switching characteristics 2 (v cc = 2.7 to 4.0 v, v ss = 0 v, t a = C20 to 85 c, unless otherwise noted) serial i/o1, serial i/o3 clock output h pulse width serial i/o1, serial i/o3 clock output l pulse width serial i/o1, serial i/o3 output delay time (note 1) serial i/o1, serial i/o3 output valid time (note 1) serial i/o1, serial i/o3 clock output rising time serial i/o1, serial i/o3 clock output falling time serial i/o2 clock output h pulse width serial i/o2 clock output l pulse width serial i/o2 output delay time serial i/o2 output valid time serial i/o2 clock output falling time cmos output rising time (note 2) cmos output falling time (note 2) t wh (s clk1 ), t wh (s clk3 ) t wl (s clk1 ), t wl (s clk3 ) t d (s clk1 -t x d1) , t d (s clk3 -t x d3) t v (s clk1 -t x d1) , t v (s clk3 -t x d3) t r (s clk1 ) , t r (s clk3 ) t f (s clk1 ), t f (s clk3 ) t wh (s clk2 ) t wl (s clk2 ) t d (s clk2 -s out2 ) t v (s clk2 -s out2 ) t f (s clk2 ) t r (cmos) t f (cmos) limits ns ns ns ns ns ns ns ns ns ns ns ns ns parameter min. t c (s clk1 )/2C50 t c (s clk1 )/2C50 C30 t c (s clk2 )/2C240 t c (s clk2 )/2C240 0 typ. 20 20 max. 350 50 50 400 50 50 50 symbol unit notes 1: when the p4 5 /t x d1 p-channel output disable bit of the uart1 control register (bit 4 of address 001b 16 ) is 0. when the p3 5 /t x d3 p-channel output disable bit of the uart3 control register (bit 4 of address 0033 16 ) is 0. 2: the x out pin is excluded. test conditions fig. 65
123 3803/3804 group single-chip 8-bit cmos microcomputer mitsubishi microcomputers fig. 103 circuit for measuring output switching characteristics (1) fig. 104 circuit for measuring output switching characteri stics (2) m e a s u r e m e n t o u t p u t p i n 1 0 0 p f c m o s o u t p u t n - c h a n n e l o p e n d r a i n o u t p u t m e a s u r e m e n t o u t p u t p i n 1 0 0 p f 1 k w
124 3803/3804 group single-chip 8-bit cmos microcomputer mitsubishi microcomputers fig. 105 timing diagram (in single-chip mode) 0 . 2 v c c t w l ( i n t ) 0 . 8 v c c t w h ( i n t ) 0 . 2 v c c 0 . 2 v c c 0 . 8 v c c 0 . 8 v c c 0 . 2 v c c t w l ( x i n ) 0 . 8 v c c t w h ( x i n ) t c ( x i n ) x i n 0 . 2 v c c 0 . 8 v c c t w ( r e s e t ) r e s e t t f t r 0 . 2 v c c t w l ( c n t r ) 0 . 8 v c c t w h ( c n t r ) t c ( c n t r ) t d ( s c l k 1 - t x d 1 ) , t d ( s c l k 2 - s o u t 2 ) , t d ( s c l k 3 - t x d 3 ) t v ( s c l k 1 - t x d 1 ) , t v ( s c l k 2 - s o u t 2 ) , t v ( s c l k 3 - t x d 3 ) t c ( s c l k 1 ) , t c ( s c l k 2 ) , t c ( s c l k 3 ) t w l ( s c l k 1 ) , t w l ( s c l k 2 ) , t w l ( s c l k 3 ) t w h ( s c l k 1 ) , t w h ( s c l k 2 ) , t w h ( s c l k 3 ) t h ( s c l k 1 - r x d 1 ) , t h ( s c l k 2 - s i n 2 ) , t h ( s c l k 3 - r x d 3 ) t s u ( r x d 1 - s c l k 1 ) , t s u ( s i n 2 - s c l k 2 ) , t s u ( r x d 3 - s c l k 3 ) t x d 1 t x d 3 s o u t 2 r x d 1 r x d 3 s i n 2 s c l k 1 s c l k 2 s c l k 3 i n t 1 , i n t 2 , in t 3 i n t 0 0 , i n t 4 0 i n t 01 , i n t 4 1 c n t r 0 , c n t r 1 , c n t r 2 t i m i n g d i a g r a m i n s i n g l e - c h i p m o d e 0 . 2 v c c t w l ( x c i n ) 0 . 8 v c c t w h ( x c i n ) t c ( x c i n ) x c i n
125 3803/3804 group single-chip 8-bit cmos microcomputer mitsubishi microcomputers symbol parameter unit table 37 multi-master i 2 c-bus bus line characteristics bus free time hold time for start condition hold time for s cl clock = 0 rising time of both s cl and s da signals data hold time hold time for s cl clock = 1 falling time of both s cl and s da signals data setup time setup time for repeated start condition setup time for stop condition t buf t hd;sta t low t r t hd;dat t high t f t su;dat t su;sta t su;sto min. max. min. max. m s m s m s ns m s m s ns ns m s m s standard clock mode high-speed clock mode note: c b = total capacitance of 1 bus line fig. 106 timing diagram of multi-master i 2 c-bus 4.7 4.0 4.7 0 4.0 250 4.7 4.0 1000 300 1.3 0.6 1.3 20+0.1c b 0 0.6 20+0.1c b 100 0.6 0.6 300 0.9 300 t b u f t h d : s t a t h d : d a t t l o w t r t f t h i g h t s u : d a t t s u : s t a t h d : s t a t s u : s t o s c l p s s r p s d a s: s t a r t c o n d i t i o n s r: r e s t a r t c o n d i t i o n p: s t o p c o n d i t i o n
126 3803/3804 group single-chip 8-bit cmos microcomputer mitsubishi microcomputers package outline qfp64-p-1414-0.80 1.11 weight(g) jedec code eiaj package code lead material alloy 42 64p6n-a plastic 64pin 14 5 14mm body qfp symbol min nom max a a 2 b c d e h e l l 1 y b 2 dimension in millimeters h d a 1 0.2 0.1 0.5 i 2 1.3 m d 14.6 m e 14.6 10 0 0.1 1.4 0.8 0.6 0.4 17.1 16.8 16.5 17.1 16.8 16.5 0.8 14.2 14.0 13.8 14.2 14.0 13.8 0.2 0.15 0.13 0.45 0.35 0.3 2.8 0 3.05 e e e e c h e 1 64 49 32 48 33 17 16 h d d m d m e a f b a 1 a 2 l 1 l y b 2 i 2 recommended mount pad detail f 64 33 32 1 e c e 1 a 2 a 1 b b 1 b 2 e l a seating plane d sdip64-p-750-1.78 weight(g) 7.9 jedec code eiaj package code lead material alloy 42 64p4b plastic 64pin 750mil sdip symbol min nom max a a 2 b b 1 b 2 c e d l dimension in millimeters a 1 0.38 ?.8 0.4 0.5 0.6 0.9 1.0 1.3 0.65 0.75 1.05 0.2 0.25 0.32 56.2 56.4 56.6 16.85 17.0 17.15 1.778 19.05 2.8 0 ?5 5.08 e e 1
127 3803/3804 group single-chip 8-bit cmos microcomputer mitsubishi microcomputers lqfp64-p-1010-0.50 weight(g) jedec code eiaj package code lead material cu alloy 64p6q-a plastic 64pin 10 5 10mm body lqfp 0.1 0.2 symbol min nom max a a 2 b c d e h e l l 1 y b 2 dimension in millimeters h d a 1 0.225 i 2 1.0 m d 10.4 m e 10.4 10 0 0.1 1.0 0.7 0.5 0.3 12.2 12.0 11.8 12.2 12.0 11.8 0.5 10.1 10.0 9.9 10.1 10.0 9.9 0.175 0.125 0.105 0.28 0.18 0.13 1.4 0 1.7 e e e h e 1 64 49 48 33 32 17 16 h d d m d m e a f y b 2 i 2 recommended mount pad lp 0.45 0.6 0.25 0.75 0.08 x a3 b x m a 1 a 2 l 1 l detail f lp a3 c e
? 1999 mitsubishi electric corp. new publication, effective sep. 1999. specifications subject to change without notice. notes regarding these materials l these materials are intended as a reference to assist our customers in the selection of the mitsubishi semiconductor product be st suited to the customers application; they do not convey any license under any intellectual property rights, or any other rights, belonging to mitsubishi electric corporation or a third party. l mitsubishi electric corporation assumes no responsibility for any damage, or infringement of any third-partys rights, originat ing in the use of any product data, diagrams, charts or circuit application examples contained in these materials. l all information contained in these materials, including product data, diagrams and charts, represent information on products at the time of publication of these materials, and are subject to change by mitsubishi electric corporation without notice due to product improvements or other reasons. it is therefore recommended that customers co ntact mitsubishi electric corporation or an authorized mitsubishi semiconductor product distributor for the latest product information before purchasing a product listed herein. l mitsubishi electric corporation semiconductors are not designed or manufactured for use in a device or system that is used unde r circumstances in which human life is potentially at stake. please contact mitsubishi electric corporation or an authorized mitsubishi semiconductor product distributor when considering the use of a pro duct contained herein for any specific purposes, such as apparatus or systems for transportation, vehicular, medical, aerospace, nuclear, or undersea repeater use. l the prior written approval of mitsubishi electric corporation is necessary to reprint or reproduce in whole or in part these ma terials. l if these products or technologies are subject to the japanese export control restrictions, they must be exported under a licens e from the japanese government and cannot be imported into a country other than the approved destination. any diversion or reexport contrary to the export control laws and regulations of japan and/or the country of destination is pro hibited. l please contact mitsubishi electric corporation or an authorized mitsubishi semiconductor product distributor for further detail s on these materials or the products contained therein. keep safety first in your circuit designs! l mitsubishi electric corporation puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble may occur with them. trouble with semiconductors may lead to personal injury, fire or property damage. remember to give due consideration to safety when making y our circuit designs, with appropriate measures such as (i) placement of substitutive, auxiliary circuits, (ii) use of non-flammable material or (iii) prevention against any malfunction or mishap. 3803/3804 group single-chip 8-bit cmos microcomputer mitsubishi microcomputers
rev. rev. no. date 0.1 first edition; only including overview. 990315 the issue including all information will be released in april. 1.0 functional descriptions are added. 990525 2.0 all pages; preliminary notice: this is... eliminated. 990909 page 9; product names are added into figure 8. page 10; product names are added into table 3. page 34; explanation of timer divider of 8-bit timers is revised. page 52; explanation of note 7 is revised. page 60; explanation of note 7 is revised. page 63; explanation of a-d converter is revised. explanations of figure 56 are partly revised. page 66; explanations of watchdog timer initial value and watchdog timer operations are revised. explanations of figure 60 are partly revised. page 67; explanation of multi-master i 2 c-bus interface is revised. explanation of note eliminated. explanations of figure 62 are partly revised. page 68; explanations of i 2 c data shift register and i 2 c address registers 0 to 2 are revised. page 69; explanation of bit 5 of i 2 c clock control register is revised. page 75; value of setup time and hold time into table 13 are revised. page 76; explanation of bit 5 of i 2 c special mode status register is added. note is added into figure 73. page 77; explanation of bit 1 of i 2 c special mode control register is added. explanation of bit 6 of i 2 c special mode control register is revised. note is added into figure 74. page 82; register contents of (21) into figure 78 is revised. page 86; explanations of figure 82 are partly revised. note 2 into figure 82 is revised. revision description list 3803/3804 group data sheet (1/2) revision description
rev. rev. no. date 2.0 page 117; table 28 is revised for only flash memory version. 990909 table 29 is added. revision description list 3803/3804 group data sheet (2/2) revision description

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